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1,181 Commits 2 Branches 432 Tags 433 MiB
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Commit Graph

20 Commits

Author SHA1 Message Date
Jared Boone
2993f7be1d SDIO: Commit optional code to run at 50MHz. 2016-07-19 11:00:31 -07:00
Jared Boone
cf5ac441ae Add CMake firmware build system. 2016-06-30 12:02:43 -07:00
Jared Boone
51b680c3bd Implement FatFs disk_ioctl MMC_GET_{TYPE,CSD}. 2016-05-09 21:55:57 -07:00
Jared Boone
95581f8c27 FatFs disk_ioctl(GET_BLOCK_SIZE) unimplemented, return correct value. 2016-05-09 21:55:06 -07:00
Jared Boone
72cc6569ca Use UM10503 (user manual) suggestion for SD delay config. 2016-05-06 15:04:53 -07:00
Jared Boone
18e40562b5 Oops, 128K is not enough. 2016-04-29 11:27:31 -07:00
Jared Boone
01fc6b9bc9 Remove redundant values in I2C struct. 2016-04-26 16:17:53 -07:00
Jared Boone
93ecf9ef82 Remove unused ldscript. 2016-04-26 16:16:04 -07:00
Jared Boone
1682f4700d Move SDC CCLK to 25MHz 
If your card can't hack it, get a new card.
 2016-04-10 17:30:12 -07:00
Jared Boone
12939a0f82 Support larger SDC LLD transactions 
Use chained DMA buffers -- limit is now 16Kbytes, adjustable by LPC_SDC_SDIO_DESCRIPTOR_COUNT. More descriptors require more stack.
 2016-04-10 17:15:59 -07:00
Jared Boone
df6593ac91 SDC: Remove commented code 2016-04-09 21:34:28 -07:00
Jared Boone
34963c7f37 SDC: Auto-off clock when no transfer. 2016-04-09 21:33:46 -07:00
Jared Boone
eb294c8e1c Add chDbgPanic for unhandled exceptions. 2016-02-27 12:05:29 -08:00
Jared Boone
9505d367c3 Add SMMULR "intrinsic". 2015-12-28 16:50:01 -08:00
Jared Boone
90cd2a6794 Improve argument and retval types for my M4 SIMD intrinsics. 2015-12-28 16:49:31 -08:00
Jared Boone
5408eb1042 Nuke duplicate peripheral pointer constants for C++ 
Turns out the reinterpret_cast idiom is no longer kosher in the standard.
 2015-12-16 21:21:45 -08:00
Jared Boone
5978c99c31 Add API to stop HAL SysTick counter. 2015-08-20 17:51:07 -07:00
Jared Boone
e9c47ff91a Remove M0 ldscript NVRAM region. 
I misunderstood the documentation. It's not NVRAM (backed up by VBAT), it just survives a deeper core sleep than other RAM does.
 2015-08-20 16:03:14 -07:00
Jared Boone
4e0de9c4ad Fix clock configuration for M4. 
M0 launches baseband, so M4 clock can be set to PLL1. Provide a way to configure that per project, set to correct values for baseband project.
 2015-08-14 12:21:49 -07:00
Jared Boone
dc6fee8370 Initial firmware commit. 2015-07-08 08:39:24 -07:00