8 Commits

Author	SHA1	Message	Date
jLynx	033c4e9a5b	Formatted code (#1007) ... * Updated style * Updated files * fixed new line * Updated spacing * File fix WIP * Updated to clang 13 * updated comment style * Removed old comment code	2023-05-19 08:16:05 +12:00
Jared Boone	e7c0fa394b	PortaPack Sync, take 2 (#215) ... * Power: Turn off additional peripheral clock branches. * Update schematic with new symbol table and KiCad standard symbols. Fix up wires. * Schematic: Update power net labels. * Schematic: Update footprint names to match library changes. * Schematic: Update header vendor and part numbers. * Schematic: Specify (arbitrary) value for PDN# net. * Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space. * Schematic: Add reference oscillator -- options for clipped sine or HCMOS output. * Schematic: Update copyright year. * Schematic: Remove CLKOUT to CPLD. It was a half-baked idea. * Schematic: Add (experimental) GPS circuit. Add note about charging circuit. Update date and revision to match PCB. * PCB: Update from schematic change: now revision 20180819. Diff was extensive due to net renumbering... * PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual. PCB: Address DRC clearance violation between via and oscillator pad. * PCB: Update copyright on drawing. * Update schematic and PCB date and revision. * gitignore: Sublime Text editor project/workspace files * Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze... * Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field. * LPC43xx: Add CGU IDIVx struct/union type. * Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use. * HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02) * MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class. * MAX V CPLD: Add BYPASS, SAMPLE support. Rename enter_isp -> enable, exit_isp -> disable. Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing. * MAX V CPLD: Reverse verify data checking logic to make it a little faster. * CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream. * Si5351: Refactor code, make one of the registers more type-safe. Clock Manager: Track selected reference clock source for later use in user interface. * Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal. It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise... * PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external. * CPLD: Add pins and logic for new PortaPack hardware feature(s). * CPLD: Bitstream to support new hardware features. * Clock Generator: Add a couple more setter methods for ClockControl registers. * Clock Manager: Use shared MCU CLKIN clock control configuration constant. * Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty. * Clock Manager: Remove redundant clock generator output enable. * Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM. * Bootstrap: Get CPU operating at max frequency as soon as possible. Update SPIFI speed comment. Make some more LPC43xx types into unions with uint32_t. * Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it. * Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream. * Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated. * Bootstrap: Consolidate clock configuration, update SPIFI rate comment. * Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward. Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out... * ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution. * PortaPack IO: Expose method to set reference oscillator enable pin. * Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader. * Pin configuration: Disable input buffers on pins that are never read. * Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution." This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03. * PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric. * PCB: Move HackRF header P9 to B.CrtYd layer. * PCB: Change a Tg reference I missed. * PCB: Update footprints for parts with mismatched CAD->tape rotation. Adjust a few layer choice and line thickness bits. * PCB: Got cold feet, switched back to rectangular pads. * PCB: Add Eco layers to be visible and Gerber output. * PCB: Use aux origin for plotting, for tidier coordinates. * PCB: Output Gerber job file, because why not? * Schematic: Correct footprints for two reference-related components. * Schematic: Remove manfuacturer and part number for DNP component. * Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination. * PCB: Update netlist and footprints from schematic. * Netlist: Updated component values, footprints. * PCB: Nudge some components and traces to address DRC clearance violations. * PCB: Allow KiCad to update zone timestamps (again?!). * PCB: Generate *all* Gerber layers. * Schematic, PCB: Update revision to 20181025. * PCB: Adjust fab layer annotations orientation and font size. * PCB: Hide mounting hole reference designators on silk layer. * PCB: Shrink U1, U3 pads to get 0.2mm space between pads. * PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options. * PCB: Revise U1 pad shape, mask, paste, thermal drills. Clearance is improved at corner pads. * PCB: Tweak U3 for better thermal pad/drill/mask/paste design. * PCB: Change solder mask color to blue. * Schematic, PCB: Update revision to 20181029. * PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math. * Update schematic * Remove unused board files. * Add LPC43xx functions. * chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits. * LPC43xx: Add MCPWM peripheral struct. * clock generator: Use recommended PLL reset register value. Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000. * GPIO: Tweak masking of SCU function. I don't remember why I thought this was necessary... * HAL: Explicitly turn on timer peripheral clocks used as systicks, during init. * SCU: Add struct to hold pin configuration. * PAL: Add functions to address The Glitch. https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/ * PAL/board: New IO initialization code Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch. * Merge M0 and M4 to eliminate need for bootstrap firmware During _early_init, detect if we're running on the M4 or M0. If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep. If M0: do all the other things. * Pins: Miscellaneous SCU configuration tweaks. * Little code clarity improvement. * bootstrap: Remove, not necessary. * Clock Manager: Large re-working to support external references. * Clock Manager: Actually store chosen clock reference Similarly-named local was covering a member and discarding the value. * Clock Manager: Reference type which contains source, frequency. * Setup: Display reference source, frequency in frequency correction screen. * LPC43xx API: Add extern "C" for use from C++. * Use LPC43xx API for SGPIO, GPDMA, I2S initialization. * I2S: Add BASE_AUDIO_CLK management. * Add MOTOCON_PWM clock/reset structure. * Serial: Fix dumb typos. * Serial: Remove extra reference operator. * Serial: Cut-and-paste error in structure type name. * Move SCU structure from PAL to LPC43xx API. It'd be nice if I gave some thought to where code should live before I commit it. * VAA power: Move code to HackRF board file It doesn't belong in PAL. * MAX5 CPLD: Add SAMPLE and EXTEST methods. * Flash image: Change packing scheme to use flash more efficiently. Application is now a single image for both M4 bootstrap and M0. Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash). * Clock Manager: Remove PLL1 power down function. * Move and rename peripherals reset function to board module. * Remove unused peripheral/clock management. * Clock Manager: Extract switch to IRC into separate function. * Clock Manager: More explicit shutdown of clocks, clock generator. * Move initialization to board module. * ChibiOS: Rename "application" board, add "baseband" board. There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup. * Clock Manager: Remove unused crystal enable/disable code. * Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown. * Reset peripherals on app shutdown. Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state). * M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0. This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown. * Audio app: Stop audio PLL on shutdown. * M4 HAL: Make LPC43XX_M4_CLK_SRC optional. This was changing the BASE_M4_CLK when a baseband was run. * LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width. * Application board: hide the peripherals_reset function, as it isn't useful except during hardware init. * Consolidate hardware init code to some degree. ClockManager is super-overloaded and murky in its purpose. Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown. * Migrate some startup code to application board. * Si5351: Use correct methods for reset(). update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown. For similar reasons, use set_clock_control() instead of setting internal state and then using the update function. * GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader. * Change application board.c to .cpp, with required dependent changes * Board: Clean up SCU configuration code/data. * I2S: Add shutdown code and use it. * LPC43xx: Consolidate a bunch of structures that had been scattered all over. ...because I'm an undisciplined coder. * I2S: Fix ordering of branch and base clock disable. Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled. * Controls: Save and expose raw navigation wheel switch state I need to do some work on debouncing and ignoring simultaneous key presses. * Controls: Add debug view for switches state. * Controls: Ignore all key presses until all keys are released. This should address some mechanical quirks of the navigation wheel used on the PortaPack. * Clock Manager: Wait for only the necessary PLL to lock. Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL. TODO: Switching PLLs may be kind of pointless now... * CMake: Pull HackRF project from GitHub and build. * CMake: Remove commented code. * CMake: Clone HackRF via HTTPS, not SSH. * CMake: Extra pause for slow post-DFU firmware boot-up. * CMake: TODO to fix SVF/XSVF file source. * CMake: Ask HackRF hackrf_usb to make DFU binary. * Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion. * Travis-CI: Update build environment to Ubuntu xenial Previously Trusty. * Travis-CI: Incorrectly structured my request for dfu-util package. I'm soooo talented. * ldscript: Mark flash, ram with correct R/W/X flags. * ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash. * Receiver: Hide PPM adjustment if clock source is not HackRF crystal. * Documentation: Update product photos and README. * Documentation: Add TCXO feature to README description. * Application: Rearrange files to match HAVOC directory structure. * Map view in AIS (#213) * Added GeoMapView to AISRecentEntryDetailView * Added autoupdate in AIS map * Revert "Map view in AIS (#213)" This reverts commit 262c030224. This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted. * Revert "Upstream merge to make new revision of PortaPack work (#206)" This reverts commit 920b98f7c9. This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks. * CPLD: Pull bitstream from HackRF project. * SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN. * CPLD: Don't load HackRF CPLD bitstream into RAM. Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary. * CPLD: Tweak clock generator config to match CPLD timing changes in HackRF. * PinConfig: Drive CPLD pins correctly. * CMake: Use jboone/hackrf master branch, now that CPLD fixes are there. * CMake: Fix HackRF CPLD SVF dependency. Build would break on the first pass, but work if you restarted make. * CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree * CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR. * CMake: Choose a CMP0005 policy to quiet CMake warnings. * Settings: Show active clock reference. Only show PPM adjustment for HackRF source. * Radio Settings: Change reference clock text color. Make consistent color with other un-editable text. TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.	2019-02-03 18:25:11 +00:00
Maescool	920b98f7c9	Upstream merge to make new revision of PortaPack work (#206) ... * Power: Turn off additional peripheral clock branches. * Update schematic with new symbol table and KiCad standard symbols. Fix up wires. * Schematic: Update power net labels. * Schematic: Update footprint names to match library changes. * Schematic: Update header vendor and part numbers. * Schematic: Specify (arbitrary) value for PDN# net. * Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space. * Schematic: Add reference oscillator -- options for clipped sine or HCMOS output. * Schematic: Update copyright year. * Schematic: Remove CLKOUT to CPLD. It was a half-baked idea. * Schematic: Add (experimental) GPS circuit. Add note about charging circuit. Update date and revision to match PCB. * PCB: Update from schematic change: now revision 20180819. Diff was extensive due to net renumbering... * PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual. PCB: Address DRC clearance violation between via and oscillator pad. * PCB: Update copyright on drawing. * Update schematic and PCB date and revision. * gitignore: Sublime Text editor project/workspace files * Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze... * Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field. * LPC43xx: Add CGU IDIVx struct/union type. * Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use. * HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02) * MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class. * MAX V CPLD: Add BYPASS, SAMPLE support. Rename enter_isp -> enable, exit_isp -> disable. Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing. * MAX V CPLD: Reverse verify data checking logic to make it a little faster. * CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream. * Si5351: Refactor code, make one of the registers more type-safe. Clock Manager: Track selected reference clock source for later use in user interface. * Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal. It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise... * PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external. * CPLD: Add pins and logic for new PortaPack hardware feature(s). * CPLD: Bitstream to support new hardware features. * Clock Generator: Add a couple more setter methods for ClockControl registers. * Clock Manager: Use shared MCU CLKIN clock control configuration constant. * Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty. * Clock Manager: Remove redundant clock generator output enable. * Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM. * Bootstrap: Get CPU operating at max frequency as soon as possible. Update SPIFI speed comment. Make some more LPC43xx types into unions with uint32_t. * Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it. * Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream. * Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated. * Bootstrap: Consolidate clock configuration, update SPIFI rate comment. * Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward. Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out... * ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution. * PortaPack IO: Expose method to set reference oscillator enable pin. * Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader. * Pin configuration: Disable input buffers on pins that are never read. * Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution." This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03. * Remove unused board files. * Add LPC43xx functions. * chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits. * LPC43xx: Add MCPWM peripheral struct. * clock generator: Use recommended PLL reset register value. Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000. * GPIO: Tweak masking of SCU function. I don't remember why I thought this was necessary... * HAL: Explicitly turn on timer peripheral clocks used as systicks, during init. * SCU: Add struct to hold pin configuration. * PAL: Add functions to address The Glitch. https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/ * PAL/board: New IO initialization code Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch. * Merge M0 and M4 to eliminate need for bootstrap firmware During _early_init, detect if we're running on the M4 or M0. If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep. If M0: do all the other things. * Pins: Miscellaneous SCU configuration tweaks. * Little code clarity improvement. * bootstrap: Remove, not necessary. * Clock Manager: Large re-working to support external references. * Fix merge conflicts	2019-01-11 06:56:21 +00:00
Jared Boone	23c340abb2	MAX V: Add shift_dr() for testing.	2017-07-18 10:53:43 -07:00
Jared Boone	dec4e41189	CPLD: Organize CPLD code into namespaces. ... Use type aliases to hide actual CPLD type (somewhat).	2017-06-02 21:57:13 -07:00
Jared Boone	22143c9543	JTAG: Remove unused methods.	2016-07-13 11:02:13 -07:00
Jared Boone	3ed1d9e24a	CPLD: Method to calculate bitstream CRC32.	2016-07-05 12:06:51 -07:00
Jared Boone	dc6fee8370	Initial firmware commit.	2015-07-08 08:39:24 -07:00