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16 commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
gullradriel
|
1dbfc50dbe
|
Stable merge v2.2.0 (#2736)
* Update README.md
Actually valid complete ali h4m link
* Fake brightness reimplementation (#2444)
* Fake brightness reimplementation
* indentation
* added call to the function which is caching the display settings values
* use cached values instead of pmem
* app manager (#2442)
* fix unset autostart
* clean up - add comments to prevent misleading
* move the app to external and with necessary changes
* replace autostart app
* Add + - buttons in Encoder dial settings (#2447)
* M10 additional parser (#2448)
* Remember previous capture settings (#2450)
* Renamed parameters in rx_capture.ini file (#2452)
* Rename settings in file to match screen
* Renamed variables for hopefully better clarity
* Navigation buttons (#2458)
* regenerate bitmap data
* pagination in submenu
* using little font so we are not eating menu buttons
* docker improvements (#2455)
* Update README.md
New metal case link
* The gerber files of the portapack H4 (#2463)
* Create README.txt
* Update README.txt
* Add files via upload
The gerber files of the portapack h4.
* delete
* Upload the gerber files for H4
* Update README.md (#2456)
Added a link to Lab401.com as a purchase option for EU customers.
(Lab401 was added as the EU exclusive distributor for the H4M - https://opensourcesdrlab.com/pages/distributors)
* Update README.md
* rename bitmaps into bmp
* disabling button on main menu, change labels and add 'icons' (#2466)
* disabling button on main menu, change labels and add 'icons'
* fix reverse order of buttons
---------
Co-authored-by: gullradriel <gullradriel@no-mail.com>
* fix for empty text prompt crash (#2468)
* added discord server information (#2471)
* Add the feature to decide rotate direction of encoder (#2472)
* Update README.md
Lab401 link with our redirection
* Fix encoder setting p.mem issue (#2475)
* Update README.md
Discord badge was broken, switching to shields.io
* Add fast flash script for sdcard switch hardware (#2480)
* fix cmake_minimum_required to 3.16 (#2499)
* fix fallthrough warning (#2497)
* Flipper tx: use file_path, example file (#2496)
* added subghz_dir
* use subghz_dir from file_path
* example file
* Externalize antenna calc and wav view (#2498)
* externalize antenna calc and wav view
* Added a tool to check if all the pictures in graphics are used in internal apps
* APRS: add frequency settings for Brazil (#2494)
* Add frequency settings for Brazil, named 'BR' that tunes to 145.570 MHz.
* Also added: Japan: 144.640 MHz (JAP), Thailand: 144.900 MHz (THA), Philippines: 144.740 MHz (PHI)
* Reordered list by increasing frequency
Co-authored-by: gullradriel <3157857+gullradriel@users.noreply.github.com>
* Added different modulations in signal generator (#2492)
* Added DSB, AM 100% mod index and AM 50% mod index. Changed UI.
* put back app in 'Utilities' (#2500)
Co-authored-by: gullradriel <gullradriel@no-mail.com>
* fix baseband (#2501)
* externalize wipe sdcard (#2502)
* Removing vim swap files (#2503)
* Removing vim swap files
* Added vim swap file to .gitignore
* Add modal to turn off screen when charging is detected (#2514)
* Moved country-specific FREQMAN files to the separate repository set up for it. (#2517)
* fix docker build warnings in dockerfile-nogit (#2518)
* Add new app "hopper" app. (#2482)
* make both jammer and hopper exist
* add example hopper payload
* example files
* swap scanner and recon app location
* Add widget preview tool (#2520)
* PoC
* opt
* opt
* Playlist editor (#2506)
* make both exist
* format
* fix focusing issue
* add example hopper payload
* fix compiler err
* clean up
* correct linker script addr
* lint
* PoC
* unknown: write_line issue
* clean up
* merge
* fix read line
* remove debug code
* fix english
* support new file
* support enter delay
* fix crash
* remove debug code
* some final tune
* Support Bug Key AKA Auto Key for OOK Editor app (#2523)
* _
* some final tune
* textual
* rename following gull's suggestion
* add cursor to font viewer app (#2528)
* Allow disable/enable waveform in Audio app to remove decoding problem on some frequencies
* Added different modulations in signal generator
* Added DSB, AM 100% mod index and AM 50% mod index.
* Changed UI.
* Added pulsed CW
* Adding Wefax demodulation mode inside Audio App (#2539)
* Adding_new_WFAX_GUI_mode_Audio_App
* Wefax_APT_demodulation_structure
* Solving REC Apt signal.wav from WFAX
* clang format issues
* correcting comments
* Breakout - The Portapack remake game rises from the pirate's lair (#2541)
* Breakout - The Portapack remake game rises from the pirate's lair
* Fixes
* Added a signature
* Trivial textual change about missing SD content (#2542)
* _
* _
* waveform fix 3 and trivial change (#2540)
* Moved games to new game menu (#2544)
* Moved games to new game menu
* There's enough games to have a menu now and I plan to make more. Having them in "Utilities" made no sense.
* Wefax warning fix modulation fix (#2543)
* changed order of modulations, changed case to avoid capture
* added missing AMAudioFMApt mode to dump pmem
* reorder demod, adding missing ones, fix warnings
* removed uneeded 'previous_modulation', renamed WFAX to AMFM to match other places
* removing uneeded 'previous_modulation' uneeded check in change_modulation
* move capture at the end so AMAUdioFMApt is matching the other arrays for position 4
* added AMFM to Recon Level and Scanner
* clang + more details in some comments
---------
Co-authored-by: gullradriel <gullradriel@no-mail.com>
* Snake (#2549)
* Create the Shopping Cart Lock app
Will demonstrate tomorrow. Don't merge until I do 😁
* Fixes for HTotoo's comments 😎
* Improved audio the best I can.
If nobody has any ideas to further improve high frequencies of the audio, the hardware may not be capable. I still need to check with line-out to better speaker to make sure it's not just the speaker, but it shouldn't be.
* Compared against baseband_api.cpp - matched some things better but still playback seems to be missing higher fq sounds
* renamed wav files to a more specific / less generic name
* indentation + using variables instead of litteral names for wav files to use
* indentation
* Made a Snake game - enjoy
* Code formatting. I always forget.
* move to keep sort order
* Update external.ld
Sorry I should have also asked if there was any reason that address ranges 0xADDA0000--0xADDD0000 were skipped in external.ld. I assumed there wasn't so I changed it to be consecutive using the same 0x10000 step as the other modules. If there is any reason to skip them then we should add a comment to note it. Of course these are all just temporary address values used for linking and get overwritten by a kludgy "search & replace" during the build process.
Resolves enhancement request #764
---------
Co-authored-by: gullradriel <gullradriel@no-mail.com>
Co-authored-by: Mark Thompson <129641948+NotherNgineer@users.noreply.github.com>
* Nested Debug menu into Utilities menu to tidy Home screen (#2551)
* rename rand pwd app (#2552)
* _
* remove wip code that forgot to add in old branch
* Moved speaker 1px to the right to match muted icon variant. (#2554)
* Stopwatch external app (#2553)
* updated bitmaps for speaker icon (#2555)
* updated bitmaps for speaker icon
* removed opera cake icon that was added by mistake
* adding missing Game menu source png
* cyan for Game menu
* regenerated icons
* Breakout icon change (#2556)
- Changed Breakout icon
- Changed Tetris icon color to green
* Snake icon change (#2557)
* Remove deprecated QR Code code (#2558)
* Setting for faster Button Repeat delays (#2559)
* Setting for faster Button Repeat delays
* Tweak fast delay times
* Tweak delay times
* Added description line and tweaked delay again
* OokBrute app opt (#2561)
* zooming_spectrum_AMFM_mode (#2565)
* Update README.md
Fixing opesourcesdrlab link
* Update README.md
Other link broken
* WeFax rx ext app (#2566)
* wf3
* Ookbrute (#2354)
* Revert "Ookbrute (#2354)"
This reverts commit
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sommermorgentraum
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0ea8453e8a
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tune output order (#2132) | ||
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sommermorgentraum
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f572b00391
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add real gcc ver chk (#2118) | ||
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Mark Thompson
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cb9fee8f08
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Modify warning text (#2066) | ||
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Mark Thompson
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2f48fc2ef9
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Disable LTO for external apps (#1886)
* Disable lto for external apps only * Modified "shared external code" checks |
||
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Mark Thompson
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0f6a9277a8
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Warning for shared external code during build (#1881) | ||
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Mark Thompson
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6a6c6d6502
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Add Checksums to Firmware & External App images (#1809)
* Pad image to 1MB and add simple checksum * Test code to verify firmware checksum * Comment out unneeded zlib * Add files via upload * Print space remaining in ROM * Append checksum to external apps too * Check external app checksums when loading * Is it 2024 already?! * Validate firmware checksum before flashing * Add files via upload * Added flash error warning to nav screen * Clang * Replaced some hard-coded values with #defines * Check FW checksum before USB serial flash too * Add files via upload |
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BehleZebub
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95d1bca9fd
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changed from python2 to python3 | ||
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Jared Boone
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e7c0fa394b |
PortaPack Sync, take 2 (#215)
* Power: Turn off additional peripheral clock branches. * Update schematic with new symbol table and KiCad standard symbols. Fix up wires. * Schematic: Update power net labels. * Schematic: Update footprint names to match library changes. * Schematic: Update header vendor and part numbers. * Schematic: Specify (arbitrary) value for PDN# net. * Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space. * Schematic: Add reference oscillator -- options for clipped sine or HCMOS output. * Schematic: Update copyright year. * Schematic: Remove CLKOUT to CPLD. It was a half-baked idea. * Schematic: Add (experimental) GPS circuit. Add note about charging circuit. Update date and revision to match PCB. * PCB: Update from schematic change: now revision 20180819. Diff was extensive due to net renumbering... * PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual. PCB: Address DRC clearance violation between via and oscillator pad. * PCB: Update copyright on drawing. * Update schematic and PCB date and revision. * gitignore: Sublime Text editor project/workspace files * Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze... * Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field. * LPC43xx: Add CGU IDIVx struct/union type. * Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use. * HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02) * MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class. * MAX V CPLD: Add BYPASS, SAMPLE support. Rename enter_isp -> enable, exit_isp -> disable. Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing. * MAX V CPLD: Reverse verify data checking logic to make it a little faster. * CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream. * Si5351: Refactor code, make one of the registers more type-safe. Clock Manager: Track selected reference clock source for later use in user interface. * Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal. It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise... * PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external. * CPLD: Add pins and logic for new PortaPack hardware feature(s). * CPLD: Bitstream to support new hardware features. * Clock Generator: Add a couple more setter methods for ClockControl registers. * Clock Manager: Use shared MCU CLKIN clock control configuration constant. * Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty. * Clock Manager: Remove redundant clock generator output enable. * Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM. * Bootstrap: Get CPU operating at max frequency as soon as possible. Update SPIFI speed comment. Make some more LPC43xx types into unions with uint32_t. * Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it. * Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream. * Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated. * Bootstrap: Consolidate clock configuration, update SPIFI rate comment. * Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward. Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out... * ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution. * PortaPack IO: Expose method to set reference oscillator enable pin. * Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader. * Pin configuration: Disable input buffers on pins that are never read. * Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution." This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03. * PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric. * PCB: Move HackRF header P9 to B.CrtYd layer. * PCB: Change a Tg reference I missed. * PCB: Update footprints for parts with mismatched CAD->tape rotation. Adjust a few layer choice and line thickness bits. * PCB: Got cold feet, switched back to rectangular pads. * PCB: Add Eco layers to be visible and Gerber output. * PCB: Use aux origin for plotting, for tidier coordinates. * PCB: Output Gerber job file, because why not? * Schematic: Correct footprints for two reference-related components. * Schematic: Remove manfuacturer and part number for DNP component. * Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination. * PCB: Update netlist and footprints from schematic. * Netlist: Updated component values, footprints. * PCB: Nudge some components and traces to address DRC clearance violations. * PCB: Allow KiCad to update zone timestamps (again?!). * PCB: Generate *all* Gerber layers. * Schematic, PCB: Update revision to 20181025. * PCB: Adjust fab layer annotations orientation and font size. * PCB: Hide mounting hole reference designators on silk layer. * PCB: Shrink U1, U3 pads to get 0.2mm space between pads. * PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options. * PCB: Revise U1 pad shape, mask, paste, thermal drills. Clearance is improved at corner pads. * PCB: Tweak U3 for better thermal pad/drill/mask/paste design. * PCB: Change solder mask color to blue. * Schematic, PCB: Update revision to 20181029. * PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math. * Update schematic * Remove unused board files. * Add LPC43xx functions. * chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits. * LPC43xx: Add MCPWM peripheral struct. * clock generator: Use recommended PLL reset register value. Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000. * GPIO: Tweak masking of SCU function. I don't remember why I thought this was necessary... * HAL: Explicitly turn on timer peripheral clocks used as systicks, during init. * SCU: Add struct to hold pin configuration. * PAL: Add functions to address The Glitch. https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/ * PAL/board: New IO initialization code Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch. * Merge M0 and M4 to eliminate need for bootstrap firmware During _early_init, detect if we're running on the M4 or M0. If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep. If M0: do all the other things. * Pins: Miscellaneous SCU configuration tweaks. * Little code clarity improvement. * bootstrap: Remove, not necessary. * Clock Manager: Large re-working to support external references. * Clock Manager: Actually store chosen clock reference Similarly-named local was covering a member and discarding the value. * Clock Manager: Reference type which contains source, frequency. * Setup: Display reference source, frequency in frequency correction screen. * LPC43xx API: Add extern "C" for use from C++. * Use LPC43xx API for SGPIO, GPDMA, I2S initialization. * I2S: Add BASE_AUDIO_CLK management. * Add MOTOCON_PWM clock/reset structure. * Serial: Fix dumb typos. * Serial: Remove extra reference operator. * Serial: Cut-and-paste error in structure type name. * Move SCU structure from PAL to LPC43xx API. It'd be nice if I gave some thought to where code should live before I commit it. * VAA power: Move code to HackRF board file It doesn't belong in PAL. * MAX5 CPLD: Add SAMPLE and EXTEST methods. * Flash image: Change packing scheme to use flash more efficiently. Application is now a single image for both M4 bootstrap and M0. Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash). * Clock Manager: Remove PLL1 power down function. * Move and rename peripherals reset function to board module. * Remove unused peripheral/clock management. * Clock Manager: Extract switch to IRC into separate function. * Clock Manager: More explicit shutdown of clocks, clock generator. * Move initialization to board module. * ChibiOS: Rename "application" board, add "baseband" board. There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup. * Clock Manager: Remove unused crystal enable/disable code. * Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown. * Reset peripherals on app shutdown. Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state). * M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0. This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown. * Audio app: Stop audio PLL on shutdown. * M4 HAL: Make LPC43XX_M4_CLK_SRC optional. This was changing the BASE_M4_CLK when a baseband was run. * LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width. * Application board: hide the peripherals_reset function, as it isn't useful except during hardware init. * Consolidate hardware init code to some degree. ClockManager is super-overloaded and murky in its purpose. Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown. * Migrate some startup code to application board. * Si5351: Use correct methods for reset(). update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown. For similar reasons, use set_clock_control() instead of setting internal state and then using the update function. * GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader. * Change application board.c to .cpp, with required dependent changes * Board: Clean up SCU configuration code/data. * I2S: Add shutdown code and use it. * LPC43xx: Consolidate a bunch of structures that had been scattered all over. ...because I'm an undisciplined coder. * I2S: Fix ordering of branch and base clock disable. Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled. * Controls: Save and expose raw navigation wheel switch state I need to do some work on debouncing and ignoring simultaneous key presses. * Controls: Add debug view for switches state. * Controls: Ignore all key presses until all keys are released. This should address some mechanical quirks of the navigation wheel used on the PortaPack. * Clock Manager: Wait for only the necessary PLL to lock. Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL. TODO: Switching PLLs may be kind of pointless now... * CMake: Pull HackRF project from GitHub and build. * CMake: Remove commented code. * CMake: Clone HackRF via HTTPS, not SSH. * CMake: Extra pause for slow post-DFU firmware boot-up. * CMake: TODO to fix SVF/XSVF file source. * CMake: Ask HackRF hackrf_usb to make DFU binary. * Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion. * Travis-CI: Update build environment to Ubuntu xenial Previously Trusty. * Travis-CI: Incorrectly structured my request for dfu-util package. I'm soooo talented. * ldscript: Mark flash, ram with correct R/W/X flags. * ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash. * Receiver: Hide PPM adjustment if clock source is not HackRF crystal. * Documentation: Update product photos and README. * Documentation: Add TCXO feature to README description. * Application: Rearrange files to match HAVOC directory structure. * Map view in AIS (#213) * Added GeoMapView to AISRecentEntryDetailView * Added autoupdate in AIS map * Revert "Map view in AIS (#213)" This reverts commit |
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Maescool
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920b98f7c9 |
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches. * Update schematic with new symbol table and KiCad standard symbols. Fix up wires. * Schematic: Update power net labels. * Schematic: Update footprint names to match library changes. * Schematic: Update header vendor and part numbers. * Schematic: Specify (arbitrary) value for PDN# net. * Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space. * Schematic: Add reference oscillator -- options for clipped sine or HCMOS output. * Schematic: Update copyright year. * Schematic: Remove CLKOUT to CPLD. It was a half-baked idea. * Schematic: Add (experimental) GPS circuit. Add note about charging circuit. Update date and revision to match PCB. * PCB: Update from schematic change: now revision 20180819. Diff was extensive due to net renumbering... * PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual. PCB: Address DRC clearance violation between via and oscillator pad. * PCB: Update copyright on drawing. * Update schematic and PCB date and revision. * gitignore: Sublime Text editor project/workspace files * Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze... * Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field. * LPC43xx: Add CGU IDIVx struct/union type. * Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use. * HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02) * MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class. * MAX V CPLD: Add BYPASS, SAMPLE support. Rename enter_isp -> enable, exit_isp -> disable. Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing. * MAX V CPLD: Reverse verify data checking logic to make it a little faster. * CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream. * Si5351: Refactor code, make one of the registers more type-safe. Clock Manager: Track selected reference clock source for later use in user interface. * Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal. It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise... * PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external. * CPLD: Add pins and logic for new PortaPack hardware feature(s). * CPLD: Bitstream to support new hardware features. * Clock Generator: Add a couple more setter methods for ClockControl registers. * Clock Manager: Use shared MCU CLKIN clock control configuration constant. * Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty. * Clock Manager: Remove redundant clock generator output enable. * Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM. * Bootstrap: Get CPU operating at max frequency as soon as possible. Update SPIFI speed comment. Make some more LPC43xx types into unions with uint32_t. * Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it. * Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream. * Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated. * Bootstrap: Consolidate clock configuration, update SPIFI rate comment. * Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward. Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out... * ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution. * PortaPack IO: Expose method to set reference oscillator enable pin. * Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader. * Pin configuration: Disable input buffers on pins that are never read. * Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution." This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03. * Remove unused board files. * Add LPC43xx functions. * chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits. * LPC43xx: Add MCPWM peripheral struct. * clock generator: Use recommended PLL reset register value. Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000. * GPIO: Tweak masking of SCU function. I don't remember why I thought this was necessary... * HAL: Explicitly turn on timer peripheral clocks used as systicks, during init. * SCU: Add struct to hold pin configuration. * PAL: Add functions to address The Glitch. https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/ * PAL/board: New IO initialization code Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch. * Merge M0 and M4 to eliminate need for bootstrap firmware During _early_init, detect if we're running on the M4 or M0. If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep. If M0: do all the other things. * Pins: Miscellaneous SCU configuration tweaks. * Little code clarity improvement. * bootstrap: Remove, not necessary. * Clock Manager: Large re-working to support external references. * Fix merge conflicts |
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furrtek
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38e506a108 |
OOK transmit is mostly working, bit durations are wrong
Simplified messages carrying data (uses shared_memory instead) Added SymField widget (bitfield, symbol field...) Added some space for baseband code BMP palette loading bugfix |
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furrtek
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79f2134d91 | Cleaned up Xylos TX, J/N works again | ||
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Jared Boone
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97ba19af24 |
Change M4 loader to use image tags.
Also finish moving HackRF binary to tagged image region. |
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Jared Boone
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4fe145b61d |
Remove application kludge to strip DFU of header.
Strip the header in in the Python SPI image generator, instead. |
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Jared Boone
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f7ced7a823 | Support Python 3.x in make_spi_image.py. | ||
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Jared Boone
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dfe0bd7366 |
Generate SPI flash image with Python, not dd/cat/head.
Addresses issue #42. Windows users now stand a chance of being able to build an image, and all these zero-byte HackRF binary issues should go away. |