Jared Boone
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df6593ac91
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SDC: Remove commented code
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2016-04-09 21:34:28 -07:00 |
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Jared Boone
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34963c7f37
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SDC: Auto-off clock when no transfer.
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2016-04-09 21:33:46 -07:00 |
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Jared Boone
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eb294c8e1c
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Add chDbgPanic for unhandled exceptions.
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2016-02-27 12:05:29 -08:00 |
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furrtek
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6e496e2b26
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Merge fixing, commit to catch up on recent files
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2016-02-04 10:27:53 +01:00 |
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furrtek
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44638e504b
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SYNC
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2016-01-31 09:34:24 +01:00 |
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furrtek
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107c212d88
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Completely useless "about" screen
Paved road for talking Xylos RX and logger
Added test button for Xylos TX
Fixed jammer crashing after loading second time
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2016-01-30 00:28:05 +01:00 |
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furrtek
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496c77fe3e
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Module loading should work again
Modules won't load if already loaded (dirty footprint hack)
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2016-01-05 20:17:55 +01:00 |
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Jared Boone
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9505d367c3
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Add SMMULR "intrinsic".
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2015-12-28 16:50:01 -08:00 |
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Jared Boone
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90cd2a6794
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Improve argument and retval types for my M4 SIMD intrinsics.
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2015-12-28 16:49:31 -08:00 |
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Jared Boone
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5408eb1042
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Nuke duplicate peripheral pointer constants for C++
Turns out the reinterpret_cast idiom is no longer kosher in the standard.
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2015-12-16 21:21:45 -08:00 |
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Jared Boone
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5978c99c31
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Add API to stop HAL SysTick counter.
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2015-08-20 17:51:07 -07:00 |
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Jared Boone
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e9c47ff91a
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Remove M0 ldscript NVRAM region.
I misunderstood the documentation. It's not NVRAM (backed up by VBAT), it just survives a deeper core sleep than other RAM does.
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2015-08-20 16:03:14 -07:00 |
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Jared Boone
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4e0de9c4ad
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Fix clock configuration for M4.
M0 launches baseband, so M4 clock can be set to PLL1. Provide a way to configure that per project, set to correct values for baseband project.
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2015-08-14 12:21:49 -07:00 |
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Jared Boone
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dc6fee8370
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Initial firmware commit.
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2015-07-08 08:39:24 -07:00 |
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