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Initial release of schematic, PCB, CPLD code.

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This commit is contained in:
Jared Boone 2015-07-16 09:32:10 -07:00
parent 154b40d3c9
commit 604389f8cd
15 changed files with 12499 additions and 0 deletions
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hardware/portapack_h1/README Normal file
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PortaPack H1 is portability add-on hardware for the HackRF One
software-defined radio (SDR).
Schematic
=========
The schematic was drawn using KiCad.
Schematic symbols are cached in the design files, but are also
available in a separate repository:
https://github.com/sharebrained/library-kicad/
PCB
===
The circuit board was designed using KiCad.
PCB footprints are cached in the design files, but are also
avaliable in a separate repository:
https://github.com/sharebrained/library-kicad/
The PCB is a four-layer design. Services such as OSHPark.com have suitable
four-layer stack ups.
CPLD
====
The CPLD bitstream is prepared using Altera Quartus tools.
The CPLD is programmed from within the PortaPack firmware, by bit-banging
the JTAG pins from the HackRF One's microcontroller.
License
=======
Copyright (C) 2013, 2014, 2015 Jared Boone, ShareBrained Technology, Inc.
These files are part of PortaPack.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING. If not, write to
the Free Software Foundation, Inc., 51 Franklin Street,
Boston, MA 02110-1301, USA.

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hardware/portapack_h1/cpld/portapack_h1_cpld.qpf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 21:24:55 April 29, 2014
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "21:24:55 April 29, 2014"
# Revisions
PROJECT_REVISION = "portapack_h1_cpld"

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hardware/portapack_h1/cpld/portapack_h1_cpld.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 21:24:55 April 29, 2014
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# portapack_h1_cpld_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX V"
set_global_assignment -name DEVICE 5M40ZE64C5
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:24:55 APRIL 29, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION 14.1.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE EQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 64
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR simulation/modelsim -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name SDC_FILE portapack_h1_cpld.sdc
set_global_assignment -name VHDL_FILE top.vhd
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
set_location_assignment PIN_46 -to LCD_DB[15]
set_location_assignment PIN_47 -to LCD_DB[14]
set_location_assignment PIN_48 -to LCD_DB[13]
set_location_assignment PIN_49 -to LCD_DB[12]
set_location_assignment PIN_50 -to LCD_DB[11]
set_location_assignment PIN_51 -to LCD_DB[10]
set_location_assignment PIN_52 -to LCD_DB[9]
set_location_assignment PIN_53 -to LCD_DB[8]
set_location_assignment PIN_54 -to LCD_DB[7]
set_location_assignment PIN_55 -to LCD_DB[6]
set_location_assignment PIN_56 -to LCD_DB[5]
set_location_assignment PIN_58 -to LCD_DB[4]
set_location_assignment PIN_59 -to LCD_DB[3]
set_location_assignment PIN_60 -to LCD_DB[2]
set_location_assignment PIN_61 -to LCD_DB[1]
set_location_assignment PIN_62 -to LCD_DB[0]
set_location_assignment PIN_44 -to LCD_RDX
set_location_assignment PIN_43 -to LCD_RS
set_location_assignment PIN_63 -to LCD_TE
set_location_assignment PIN_45 -to LCD_WRX
set_location_assignment PIN_10 -to SW_D
set_location_assignment PIN_28 -to SW_L
set_location_assignment PIN_9 -to SW_R
set_location_assignment PIN_11 -to SW_ROT_A
set_location_assignment PIN_12 -to SW_ROT_B
set_location_assignment PIN_13 -to SW_SEL
set_location_assignment PIN_25 -to SW_U
set_location_assignment PIN_1 -to TP_D
set_location_assignment PIN_2 -to TP_L
set_location_assignment PIN_64 -to TP_R
set_location_assignment PIN_3 -to TP_U
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_D
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_L
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_R
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_ROT_A
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_ROT_B
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_SEL
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_U
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_D
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_L
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_R
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_U
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[15]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[14]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[13]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[12]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[11]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[10]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[9]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[8]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[7]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[6]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[5]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[4]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[3]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[2]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[1]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_RDX
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_RS
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_TE
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_WRX
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH top_tb -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME top_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME uut -section_id top_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME top_tb -section_id top_tb
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "500 ns" -section_id top_tb
set_global_assignment -name EDA_TEST_BENCH_FILE top_tb.vhd -section_id top_tb
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "BSDL (Boundary Scan)"
set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR /home/jboone/src/portapack/portapack_hackrf/hardware/portapack_h1/cpld -section_id eda_board_design_boundary_scan
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION POST_CONFIG -section_id eda_board_design_boundary_scan
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name GENERATE_RBF_FILE OFF
set_global_assignment -name GENERATE_SVF_FILE ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH BUS-HOLD"
set_location_assignment PIN_38 -to LCD_RESETX
set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_RESETX
set_location_assignment PIN_18 -to MCU_D[7]
set_location_assignment PIN_19 -to MCU_D[6]
set_location_assignment PIN_21 -to MCU_D[5]
set_location_assignment PIN_20 -to MCU_D[4]
set_location_assignment PIN_22 -to MCU_D[3]
set_location_assignment PIN_24 -to MCU_D[2]
set_location_assignment PIN_27 -to MCU_D[1]
set_location_assignment PIN_26 -to MCU_D[0]
set_location_assignment PIN_33 -to MCU_ADDR
set_location_assignment PIN_42 -to MCU_DIR
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_ADDR
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_DIR
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_D
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_L
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_R
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_U
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_ROT_B
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_SEL
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_ROT_A
set_location_assignment PIN_31 -to MCU_ROT_A
set_location_assignment PIN_30 -to MCU_ROT_B
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_ROT_A
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_ROT_B
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[15]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[14]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_RDX
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_RESETX
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_RS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_TE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_WRX
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_ADDR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_DIR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_ROT_A
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_ROT_B
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_D
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_L
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_R
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_ROT_A
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_ROT_B
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_SEL
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_U
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_D
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_L
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_R
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_U
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[15]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[14]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[13]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[12]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[11]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[10]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[9]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[8]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[7]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[6]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[5]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[4]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[3]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[2]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[1]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[0]
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_RDX
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_RESETX
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_RS
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_TE
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_WRX
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_ADDR
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[7]
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[6]
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[5]
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[4]
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[3]
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[2]
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[1]
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[0]
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_DIR
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_ROT_A
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_ROT_B
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_D
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_L
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_R
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_ROT_A
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_ROT_B
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_SEL
set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_U
set_instance_assignment -name SLOW_SLEW_RATE ON -to TP_D
set_instance_assignment -name SLOW_SLEW_RATE ON -to TP_L
set_instance_assignment -name SLOW_SLEW_RATE ON -to TP_R
set_instance_assignment -name SLOW_SLEW_RATE ON -to TP_U
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON
set_global_assignment -name IOBANK_VCCIO 1.8V -section_id 2
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1
set_instance_assignment -name PCI_IO OFF -to MCU_DIR
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER ON
set_location_assignment PIN_4 -to LCD_BACKLIGHT
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LCD_BACKLIGHT
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_BACKLIGHT
set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_BACKLIGHT
set_instance_assignment -name PCI_IO OFF -to LCD_BACKLIGHT
set_location_assignment PIN_34 -to MCU_LCD_RD
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_LCD_RD
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_LCD_RD
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_LCD_RD
set_instance_assignment -name PCI_IO OFF -to MCU_LCD_RD
set_location_assignment PIN_40 -to MCU_LCD_WR
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_LCD_WR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_LCD_WR
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_LCD_WR
set_instance_assignment -name PCI_IO OFF -to MCU_LCD_WR
set_location_assignment PIN_32 -to MCU_IO_STBX
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_IO_STBX
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_IO_STBX
set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_IO_STBX
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TP_R
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TP_D
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TP_L
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TP_U

116
hardware/portapack_h1/cpld/portapack_h1_cpld.sdc Normal file
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## Generated SDC file "portapack_hackrf_one_cpld.sdc"
## Copyright (C) 1991-2014 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
## DATE "Sat May 3 10:22:18 2014"
##
## DEVICE "5M40ZE64C5"
##
# RS = 0, D = DB[15:8]
# wait max(tast = 0 ns, CPLD setup = ?)
# WR = 0, D = DB[7:0]
# wait max(CPLD )
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
set mcu_clk_period 4.9
set lcd_data_wr_setup 10.0
set lcd_data_wr_hold 10.0
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {MCU_STROBE} -period 66.000 -waveform { 0.000 33.000 } [get_ports {MCU_STROBE}]
#create_clock -name strobe_virt -period 66.000
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
#set_input_delay -clock strobe_virt [get_ports {D[*]}]
#**************************************************************
# Set Output Delay
#**************************************************************
#**************************************************************
# Set Clock Groups
#**************************************************************
#**************************************************************
# Set False Path
#**************************************************************
set_false_path -from [get_clocks {MCU_STROBE}] -to [get_ports {TP_D TP_L TP_R TP_U}]
set_false_path -from [get_ports {SW_D SW_L SW_R SW_ROT_A SW_ROT_B SW_SEL SW_U}] -to [get_ports {MCU_D[*]}]
#**************************************************************
# Set Multicycle Path
#**************************************************************
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

170
hardware/portapack_h1/cpld/top.vhd Normal file
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--
-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc.
--
-- This file is part of PortaPack.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
MCU_D : inout std_logic_vector(7 downto 0);
MCU_DIR : in std_logic;
MCU_IO_STBX : in std_logic;
MCU_LCD_WR : in std_logic;
MCU_ADDR : in std_logic;
MCU_ROT_A : out std_logic;
MCU_ROT_B : out std_logic;
MCU_LCD_RD : in std_logic;
TP_U : out std_logic;
TP_D : out std_logic;
TP_L : out std_logic;
TP_R : out std_logic;
SW_SEL : in std_logic;
SW_ROT_A : in std_logic;
SW_ROT_B : in std_logic;
SW_U : in std_logic;
SW_D : in std_logic;
SW_L : in std_logic;
SW_R : in std_logic;
LCD_RESETX : out std_logic;
LCD_RS : out std_logic;
LCD_WRX : out std_logic;
LCD_RDX : out std_logic;
LCD_DB : inout std_logic_vector(15 downto 0);
LCD_TE : in std_logic;
LCD_BACKLIGHT : out std_logic
);
end top;
architecture rtl of top is
signal switches : std_logic_vector(7 downto 0);
type data_direction_t is (from_mcu, to_mcu);
signal data_dir : data_direction_t;
signal mcu_data_out_lcd : std_logic_vector(7 downto 0);
signal mcu_data_out_io : std_logic_vector(7 downto 0);
signal mcu_data_out : std_logic_vector(7 downto 0);
signal mcu_data_in : std_logic_vector(7 downto 0);
signal lcd_data_in : std_logic_vector(15 downto 0);
signal lcd_data_in_mux : std_logic_vector(7 downto 0);
signal lcd_data_out : std_logic_vector(15 downto 0);
signal lcd_data_in_q : std_logic_vector(7 downto 0) := (others => '0');
signal lcd_data_out_q : std_logic_vector(7 downto 0) := (others => '0');
signal tp_q : std_logic_vector(7 downto 0) := (others => '0');
signal lcd_reset_q : std_logic := '1';
signal lcd_backlight_q : std_logic := '0';
signal dir_read : boolean;
signal dir_write : boolean;
signal lcd_read_strobe : boolean;
signal lcd_write_strobe : boolean;
signal lcd_write : boolean;
signal io_strobe : boolean;
signal io_read_strobe : boolean;
signal io_write_strobe : boolean;
begin
-- I/O data
switches <= LCD_TE & not SW_ROT_B & not SW_ROT_A & not SW_SEL & not SW_U & not SW_D & not SW_L & not SW_R;
TP_U <= tp_q(3) when tp_q(7) = '1' else 'Z';
TP_D <= tp_q(2) when tp_q(6) = '1' else 'Z';
TP_L <= tp_q(1) when tp_q(5) = '1' else 'Z';
TP_R <= tp_q(0) when tp_q(4) = '1' else 'Z';
LCD_BACKLIGHT <= lcd_backlight_q;
MCU_ROT_A <= LCD_TE; -- not SW_ROT_A;
MCU_ROT_B <= '0'; -- not SW_ROT_B;
-- State management
data_dir <= to_mcu when MCU_DIR = '1' else from_mcu;
dir_read <= (data_dir = to_mcu);
dir_write <= (data_dir = from_mcu);
io_strobe <= (MCU_IO_STBX = '0');
io_read_strobe <= io_strobe and dir_read;
io_write_strobe <= io_strobe and dir_write;
lcd_read_strobe <= (MCU_LCD_RD = '1');
lcd_write_strobe <= (MCU_LCD_WR = '1');
lcd_write <= not lcd_read_strobe;
-- LCD interface
LCD_RS <= MCU_ADDR;
LCD_RDX <= not MCU_LCD_RD;
LCD_WRX <= not MCU_LCD_WR;
lcd_data_out <= lcd_data_out_q & mcu_data_in;
lcd_data_in <= LCD_DB;
LCD_DB <= lcd_data_out when lcd_write else (others => 'Z');
LCD_RESETX <= not lcd_reset_q;
-- MCU interface
mcu_data_out_lcd <= lcd_data_in(15 downto 8) when lcd_read_strobe else lcd_data_in_q;
mcu_data_out_io <= switches;
mcu_data_out <= mcu_data_out_io when io_read_strobe else mcu_data_out_lcd;
mcu_data_in <= MCU_D;
MCU_D <= mcu_data_out when dir_read else (others => 'Z');
-- Synchronous behaviors:
-- LCD write: Capture LCD high byte on LCD_WRX falling edge.
process(MCU_LCD_WR, mcu_data_in)
begin
if rising_edge(MCU_LCD_WR) then
lcd_data_out_q <= mcu_data_in;
end if;
end process;
-- LCD read: Capture LCD low byte on LCD_RD falling edge.
process(MCU_LCD_RD, lcd_data_in)
begin
if falling_edge(MCU_LCD_RD) then
lcd_data_in_q <= lcd_data_in(7 downto 0);
end if;
end process;
-- I/O write (to resistive touch panel): Capture data from
-- MCU and hold on TP pins until further notice.
process(MCU_IO_STBX, dir_write, mcu_data_in, MCU_ADDR)
begin
if rising_edge(MCU_IO_STBX) and dir_write then
if MCU_ADDR = '0' then
tp_q <= mcu_data_in;
else
lcd_reset_q <= mcu_data_in(0);
lcd_backlight_q <= mcu_data_in(7);
end if;
end if;
end process;
end rtl;

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hardware/portapack_h1/cpld/top_tb.vhd Normal file
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--
-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc.
--
-- This file is part of PortaPack.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library ieee;
use ieee.std_logic_1164.all;
entity top_tb is
end top_tb;
architecture behavior of top_tb is
component top
port (
MCU_D : inout std_logic_vector(7 downto 0);
MCU_DIR : in std_logic;
MCU_MODE : in std_logic;
MCU_STROBE : in std_logic;
MCU_ADDR : in std_logic;
TP_U : out std_logic;
TP_D : out std_logic;
TP_L : out std_logic;
TP_R : out std_logic;
SW_SEL : in std_logic;
SW_ROT_A : in std_logic;
SW_ROT_B : in std_logic;
SW_U : in std_logic;
SW_D : in std_logic;
SW_L : in std_logic;
SW_R : in std_logic;
LCD_RESETX : out std_logic;
LCD_RS : out std_logic;
LCD_WRX : out std_logic;
LCD_RDX : out std_logic;
LCD_DB : inout std_logic_vector(17 downto 0);
LCD_TE : in std_logic
);
end component;
signal mcu_d : std_logic_vector(7 downto 0);
signal mcu_strobe : std_logic;
signal mcu_dir : std_logic;
signal mcu_mode : std_logic;
signal mcu_addr : std_logic;
signal tp_u : std_logic;
signal tp_d : std_logic;
signal tp_l : std_logic;
signal tp_r : std_logic;
signal sw_sel : std_logic;
signal sw_rot_a : std_logic;
signal sw_rot_b : std_logic;
signal sw_u : std_logic;
signal sw_d : std_logic;
signal sw_l : std_logic;
signal sw_r : std_logic;
signal lcd_resetx : std_logic;
signal lcd_rs : std_logic;
signal lcd_wrx : std_logic;
signal lcd_rdx : std_logic;
signal lcd_db : std_logic_vector(17 downto 0);
signal lcd_te : std_logic := '0';
begin
uut : top
port map (
MCU_D => mcu_d,
MCU_STROBE => mcu_strobe,
MCU_DIR => mcu_dir,
MCU_MODE => mcu_mode,
MCU_ADDR => mcu_addr,
TP_U => tp_u,
TP_D => tp_d,
TP_L => tp_l,
TP_R => tp_r,
SW_SEL => sw_sel,
SW_ROT_A => sw_rot_a,
SW_ROT_B => sw_rot_b,
SW_U => sw_u,
SW_D => sw_d,
SW_L => sw_l,
SW_R => sw_r,
LCD_RESETX => lcd_resetx,
LCD_RS => lcd_rs,
LCD_WRX => lcd_wrx,
LCD_RDX => lcd_rdx,
LCD_DB => lcd_db,
LCD_TE => lcd_te
);
stimulus: process is
begin
sw_sel <= '0';
sw_rot_a <= '0';
sw_rot_b <= '0';
sw_u <= '0';
sw_d <= '0';
sw_l <= '0';
sw_r <= '0';
mcu_d <= (others => 'Z');
mcu_mode <= '1';
mcu_dir <= '1';
mcu_addr <= '1';
mcu_strobe <= '1';
wait for 50.0 ns;
-- Write to resistive touch panel
mcu_mode <= '0'; -- Target: I/O
mcu_dir <= '0'; -- Direction: MCU -> CPLD
mcu_addr <= '0'; -- LCD reset signal
wait for 19.6 ns; -- 4 cycles: Wait for CPLD D to reach Hi-Z
mcu_d <= "11000101";
wait for 14.7 ns; -- 3 cycles: Setup time on D before STROBE.
mcu_strobe <= '0';
wait for 9.8 ns; -- 2 cycles
mcu_strobe <= '1';
wait for 49.0 ns;
-- Write to LCD (command, then 16-bit data)
mcu_mode <= '1'; -- Target: LCD
mcu_dir <= '0'; -- Direction: MCU -> CPLD
mcu_addr <= '0'; -- Address: RS = 0 (command)
wait for 19.6 ns; -- 4 cycles: Wait for CPLD D to reach Hi-Z
mcu_d <= "10100101";
wait for 14.7 ns; -- 3 cycles: Setup time on D before STROBE.
mcu_strobe <= '0';
wait for 9.8 ns; -- 2 cycles
mcu_d <= "00001111";
wait for 24.5 ns; -- 5 cycles: Prop from D to LCD_DB[7:0], WRX# minimum low time.
mcu_strobe <= '1';
wait for 9.8 ns; -- 2 cycles: Part of prop from STROBE to LCD_WRX, delay to keep RS after WRX deassert.
mcu_addr <= '1'; -- Address: RS = 1 (data)
wait for 9.8 ns; -- 2 cycles: Part of prop from STROBE to LCD_WRX.
mcu_d <= "01011010";
wait for 14.7 ns; -- 3 cycles: Setup time on D before STROBE.
mcu_strobe <= '0';
wait for 9.8 ns; -- 2 cycles
mcu_d <= "11110000";
wait for 24.5 ns; -- 5 cycles: Prop from D to LCD_DB[7:0], WRX# minimum low time.
mcu_strobe <= '1';
wait for 19.6 ns; -- 4 cycles: Prop from STROBE to LCD_WRX.
mcu_d <= "01010101";
wait for 14.7 ns; -- 3 cycles: Setup time on D before STROBE.
mcu_strobe <= '0';
wait for 9.8 ns; -- 2 cycles
mcu_d <= "10101010";
wait for 24.5 ns; -- 5 cycles: Prop from D to LCD_DB[7:0], WRX# minimum low time.
mcu_strobe <= '1';
wait for 19.6 ns; -- 4 cycles: Prop from STROBE to LCD_WRX.
-- Read from switches
mcu_d <= (others => 'Z');
mcu_mode <= '0'; -- Target: I/O
mcu_dir <= '1'; -- Direction: MCU <- CPLD
wait for 49.0 ns;
end process;
end architecture behavior;

1559
hardware/portapack_h1/hackrf_if.sch Normal file
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656
hardware/portapack_h1/lcd_sw_sd.sch Normal file
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EESchema Schematic File Version 2
LIBS:hackrf_expansion
LIBS:wolfson
LIBS:passive
LIBS:lcd_kingtech
LIBS:power
LIBS:io_expander
LIBS:trs_jack
LIBS:battery
LIBS:mosfet
LIBS:microphone
LIBS:sd
LIBS:ck
LIBS:altera
LIBS:regulator
LIBS:tp
LIBS:header
LIBS:hole
LIBS:sharebrained
LIBS:fiducial
LIBS:portapack_h1-cache
EELAYER 24 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 3 4
Title "PortaPack H1"
Date "13 Oct 2014"
Rev "20140826"
Comp "ShareBrained Technology, Inc."
Comment1 "Copyright © 2014 Jared Boone"
Comment2 "License: GNU General Public License, version 2"
Comment3 ""
Comment4 ""
$EndDescr
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U 1 1 53A8C6E2
P 3100 6700
F 0 "#PWR049" H 3100 6700 30 0001 C CNN
F 1 "GND" H 3100 6630 30 0001 C CNN
F 2 "" H 3100 6700 60 0000 C CNN
F 3 "" H 3100 6700 60 0000 C CNN
1 3100 6700
0 1 1 0
$EndComp
$Comp
L C C27
U 1 1 53AA73CE
P 2800 7100
F 0 "C27" H 2850 7200 50 0000 L CNN
F 1 "100N" H 2850 7000 50 0000 L CNN
F 2 "" H 2800 7100 60 0000 C CNN
F 3 "" H 2800 7100 60 0000 C CNN
F 4 "Murata" H 2800 7100 60 0001 C CNN "Mfr"
F 5 "GRM155R61A104KA01" H 2800 7100 60 0001 C CNN "Part"
1 2800 7100
-1 0 0 -1
$EndComp
$Comp
L GND #PWR050
U 1 1 53A8C6EF
P 2400 7400
F 0 "#PWR050" H 2400 7400 30 0001 C CNN
F 1 "GND" H 2400 7330 30 0001 C CNN
F 2 "" H 2400 7400 60 0000 C CNN
F 3 "" H 2400 7400 60 0000 C CNN
1 2400 7400
1 0 0 -1
$EndComp
$Comp
L GND #PWR051
U 1 1 53A8C6F5
P 4200 7200
F 0 "#PWR051" H 4200 7200 30 0001 C CNN
F 1 "GND" H 4200 7130 30 0001 C CNN
F 2 "" H 4200 7200 60 0000 C CNN
F 3 "" H 4200 7200 60 0000 C CNN
1 4200 7200
1 0 0 -1
$EndComp
$Comp
L CK_TSWB-3N-CB SW1
U 1 1 53A8C6FD
P 2500 1450
F 0 "SW1" H 2500 2050 60 0000 C CNN
F 1 "CK_TSWB-3N-CB" H 2500 850 60 0000 C CNN
F 2 "" H 2500 1450 60 0000 C CNN
F 3 "" H 2500 1450 60 0000 C CNN
F 4 "C&K" H 2500 1450 60 0001 C CNN "Mfr"
F 5 "TSWB-3N-CB111 LFS" H 2500 1450 60 0001 C CNN "Part"
1 2500 1450
1 0 0 -1
$EndComp
$Comp
L GND #PWR052
U 1 1 53A8C70A
P 1400 2000
F 0 "#PWR052" H 1400 2000 30 0001 C CNN
F 1 "GND" H 1400 1930 30 0001 C CNN
F 2 "" H 1400 2000 60 0000 C CNN
F 3 "" H 1400 2000 60 0000 C CNN
1 1400 2000
1 0 0 -1
$EndComp
$Comp
L GND #PWR053
U 1 1 53A8C710
P 3600 2000
F 0 "#PWR053" H 3600 2000 30 0001 C CNN
F 1 "GND" H 3600 1930 30 0001 C CNN
F 2 "" H 3600 2000 60 0000 C CNN
F 3 "" H 3600 2000 60 0000 C CNN
1 3600 2000
1 0 0 -1
$EndComp
$Comp
L GND #PWR054
U 1 1 53A8C716
P 4000 7200
F 0 "#PWR054" H 4000 7200 30 0001 C CNN
F 1 "GND" H 4000 7130 30 0001 C CNN
F 2 "" H 4000 7200 60 0000 C CNN
F 3 "" H 4000 7200 60 0000 C CNN
1 4000 7200
1 0 0 -1
$EndComp
$Comp
L C C26
U 1 1 53A8C71C
P 2400 7100
F 0 "C26" H 2450 7200 50 0000 L CNN
F 1 "10U" H 2450 7000 50 0000 L CNN
F 2 "" H 2400 7100 60 0000 C CNN
F 3 "" H 2400 7100 60 0000 C CNN
F 4 "Murata" H 2400 7100 60 0001 C CNN "Mfr"
F 5 "GRM21BR61A106KE19" H 2400 7100 60 0001 C CNN "Part"
1 2400 7100
-1 0 0 -1
$EndComp
$Comp
L GND #PWR055
U 1 1 53A8C722
P 2800 7400
F 0 "#PWR055" H 2800 7400 30 0001 C CNN
F 1 "GND" H 2800 7330 30 0001 C CNN
F 2 "" H 2800 7400 60 0000 C CNN
F 3 "" H 2800 7400 60 0000 C CNN
1 2800 7400
1 0 0 -1
$EndComp
$Comp
L +3.3V #PWR056
U 1 1 53A8C728
P 2800 5700
F 0 "#PWR056" H 2800 5660 30 0001 C CNN
F 1 "+3.3V" H 2800 5810 30 0000 C CNN
F 2 "" H 2800 5700 60 0000 C CNN
F 3 "" H 2800 5700 60 0000 C CNN
1 2800 5700
1 0 0 -1
$EndComp
Wire Wire Line
2400 6100 2400 6900
Wire Wire Line
2800 7300 2800 7400
Connection ~ 2800 6100
Wire Wire Line
2800 5700 2800 6900
Wire Wire Line
2200 5800 3200 5800
Wire Wire Line
2200 5900 3200 5900
Wire Wire Line
2200 6000 3200 6000
Wire Wire Line
2200 6200 3200 6200
Wire Wire Line
2200 6400 3200 6400
Wire Wire Line
2200 6500 3200 6500
Wire Wire Line
3200 6300 3100 6300
Wire Wire Line
2400 6100 3200 6100
Wire Wire Line
2400 7300 2400 7400
Wire Wire Line
4200 7100 4200 7200
Wire Wire Line
1400 1000 1500 1000
Wire Wire Line
1400 1100 1500 1100
Wire Wire Line
1400 1200 1500 1200
Wire Wire Line
3500 1000 3600 1000
Wire Wire Line
3600 1100 3500 1100
Wire Wire Line
3600 1200 3500 1200
Wire Wire Line
3600 1300 3500 1300
Wire Wire Line
3500 1900 3600 1900
Wire Wire Line
3600 1900 3600 2000
Wire Wire Line
1500 1900 1400 1900
Wire Wire Line
1400 1900 1400 2000
Wire Wire Line
4000 7100 4000 7200
$Comp
L KINGTECH_DW0240A2BZ_PANEL LCD1
U 1 1 53A8C752
P 8000 4600
F 0 "LCD1" H 8000 5650 60 0000 C CNN
F 1 "KINGTECH_DW0240A2BZ_PANEL" H 8000 3650 60 0000 C CNN
F 2 "" H 8000 4600 60 0000 C CNN
F 3 "" H 8000 4600 60 0000 C CNN
1 8000 4600
1 0 0 -1
$EndComp
Wire Bus Line
8800 2900 8900 2900
Wire Bus Line
8900 2900 8900 4700
Entry Wire Line
8900 3200 9000 3300
Entry Wire Line
8900 3300 9000 3400
Entry Wire Line
8900 3400 9000 3500
Entry Wire Line
8900 3500 9000 3600
Entry Wire Line
8900 3600 9000 3700
Entry Wire Line
8900 3700 9000 3800
Entry Wire Line
8900 3800 9000 3900
Entry Wire Line
8900 3900 9000 4000
Entry Wire Line
8900 4000 9000 4100
Entry Wire Line
8900 4100 9000 4200
Entry Wire Line
8900 4200 9000 4300
Entry Wire Line
8900 4300 9000 4400
Entry Wire Line
8900 4400 9000 4500
Entry Wire Line
8900 4500 9000 4600
Entry Wire Line
8900 4600 9000 4700
Entry Wire Line
8900 4700 9000 4800
Text HLabel 8800 2900 0 60 BiDi ~ 0
LCD_DB[15..0]
Text HLabel 9600 2100 0 60 Input ~ 0
LCD_RS
Text HLabel 9600 2200 0 60 Input ~ 0
LCD_RD#
Text HLabel 9600 2500 0 60 Input ~ 0
LCD_WR#
Text HLabel 8200 2000 0 60 Input ~ 0
LCD_RESET#
Text HLabel 8200 1000 0 60 Input ~ 0
LCD_BACKLIGHT
Text HLabel 9500 4900 0 60 Output ~ 0
LCD_TE
Text HLabel 9500 5200 0 60 BiDi ~ 0
TP_R
Text HLabel 9500 5300 0 60 BiDi ~ 0
TP_D
Text HLabel 9500 5400 0 60 BiDi ~ 0
TP_L
Text HLabel 9500 5500 0 60 BiDi ~ 0
TP_U
Text HLabel 1400 1000 0 60 Output ~ 0
SW_SEL
Text HLabel 1400 1100 0 60 Output ~ 0
SW_ROT_A
Text HLabel 1400 1200 0 60 Output ~ 0
SW_ROT_B
Text HLabel 3600 1000 2 60 Output ~ 0
SW_D
Text HLabel 3600 1100 2 60 Output ~ 0
SW_R
Text HLabel 3600 1200 2 60 Output ~ 0
SW_U
Text HLabel 3600 1300 2 60 Output ~ 0
SW_L
Text HLabel 2200 5800 0 60 BiDi ~ 0
SD_DAT2
Text HLabel 2200 5900 0 60 BiDi ~ 0
SD_DAT3
Text HLabel 2200 6000 0 60 BiDi ~ 0
SD_CMD
Text HLabel 2200 6200 0 60 Input ~ 0
SD_CLK
Text HLabel 2200 6400 0 60 BiDi ~ 0
SD_DAT0
Text HLabel 2200 6500 0 60 BiDi ~ 0
SD_DAT1
Text HLabel 2200 6800 0 60 Output ~ 0
SD_CD
Wire Wire Line
9800 3100 9900 3100
Connection ~ 9800 2900
Wire Wire Line
9800 3200 9900 3200
Connection ~ 9800 3100
Wire Wire Line
9900 2400 9800 2400
Wire Wire Line
9900 2300 9800 2300
Connection ~ 9800 2400
Wire Wire Line
3200 6800 2200 6800
Wire Wire Line
3200 6700 3100 6700
$Comp
L MOSFET_N Q1
U 1 1 53C5B6EB
P 8700 950
F 0 "Q1" H 8700 801 40 0000 R CNN
F 1 "MOSFET_N" H 8700 1100 40 0000 R CNN
F 2 "" H 8570 1052 29 0000 C CNN
F 3 "" H 8700 950 60 0000 C CNN
F 4 "NXP" H 8700 950 60 0001 C CNN "Mfr"
F 5 "2N7002P,215" H 8700 950 60 0001 C CNN "Part"
1 8700 950
1 0 0 -1
$EndComp
$Comp
L GND #PWR057
U 1 1 53C5B707
P 8800 1250
F 0 "#PWR057" H 8800 1250 30 0001 C CNN
F 1 "GND" H 8800 1180 30 0001 C CNN
F 2 "" H 8800 1250 60 0000 C CNN
F 3 "" H 8800 1250 60 0000 C CNN
1 8800 1250
1 0 0 -1
$EndComp
Wire Wire Line
8800 1150 8800 1250
Wire Wire Line
9900 1700 9700 1700
Wire Wire Line
8200 1000 8500 1000
Wire Wire Line
8300 1000 8300 1100
Connection ~ 8300 1000
$Comp
L GND #PWR058
U 1 1 53C5B8B4
P 8300 1700
F 0 "#PWR058" H 8300 1700 30 0001 C CNN
F 1 "GND" H 8300 1630 30 0001 C CNN
F 2 "" H 8300 1700 60 0000 C CNN
F 3 "" H 8300 1700 60 0000 C CNN
1 8300 1700
1 0 0 -1
$EndComp
Wire Wire Line
8300 1600 8300 1700
Wire Wire Line
8800 750 8800 600
Wire Wire Line
8800 600 9800 600
Wire Wire Line
9800 600 9800 1600
$EndSCHEMATC

717
hardware/portapack_h1/portapack_h1.cmp Normal file
View File

@ -0,0 +1,717 @@
Cmp-Mod V01 Created by CvPcb (2014-03-01 BZR 4730)-product date = Tuesday, August 26, 2014 'AMt' 09:05:06 AM
BeginCmp
TimeStamp = /53A8C780/53A8D535;
Reference = BT1;
ValeurCmp = BATTERY;
IdModule = bat_coin:MPD_BU2032SM-BT-G;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C6A5;
Reference = C2;
ValeurCmp = 100N;
IdModule = ipc_capc:IPC_CAPC1005X55N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C69F;
Reference = C3;
ValeurCmp = 100N;
IdModule = ipc_capc:IPC_CAPC1005X55N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C6B1;
Reference = C4;
ValeurCmp = 100N;
IdModule = ipc_capc:IPC_CAPC1005X55N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C6AB;
Reference = C5;
ValeurCmp = 100N;
IdModule = ipc_capc:IPC_CAPC1005X55N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C687;
Reference = C6;
ValeurCmp = 100N;
IdModule = ipc_capc:IPC_CAPC1005X55N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C70E;
Reference = C7;
ValeurCmp = 10U;
IdModule = ipc_capc:IPC_CAPC2012X140N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C6F6;
Reference = C8;
ValeurCmp = 10U;
IdModule = ipc_capc:IPC_CAPC2012X140N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C708;
Reference = C9;
ValeurCmp = 10U;
IdModule = ipc_capc:IPC_CAPC2012X140N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C68D;
Reference = C10;
ValeurCmp = 100N;
IdModule = ipc_capc:IPC_CAPC1005X55N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C72C;
Reference = C11;
ValeurCmp = 10U;
IdModule = ipc_capc:IPC_CAPC2012X140N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C6F0;
Reference = C12;
ValeurCmp = 10U;
IdModule = ipc_capc:IPC_CAPC2012X140N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C720;
Reference = C13;
ValeurCmp = 10U;
IdModule = ipc_capc:IPC_CAPC2012X140N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53AF1137;
Reference = C14;
ValeurCmp = 220P;
IdModule = ipc_capc:IPC_CAPC1608X95N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53AF112C;
Reference = C15;
ValeurCmp = 220P;
IdModule = ipc_capc:IPC_CAPC1608X95N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53AF15D9;
Reference = C16;
ValeurCmp = 1U;
IdModule = ipc_capae:IPC_CAPAE430X540N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53AF15E8;
Reference = C17;
ValeurCmp = 1U;
IdModule = ipc_capae:IPC_CAPAE430X540N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C256;
Reference = C18;
ValeurCmp = 220U;
IdModule = ipc_capae:IPC_CAPAE830X620N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C25E;
Reference = C19;
ValeurCmp = 220U;
IdModule = ipc_capae:IPC_CAPAE830X620N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53AF2762;
Reference = C20;
ValeurCmp = 10U;
IdModule = ipc_capae:IPC_CAPAE430X540N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53AF2753;
Reference = C21;
ValeurCmp = 10U;
IdModule = ipc_capae:IPC_CAPAE430X540N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C27E;
Reference = C22;
ValeurCmp = 220P;
IdModule = ipc_capc:IPC_CAPC1608X95N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C284;
Reference = C23;
ValeurCmp = 220P;
IdModule = ipc_capc:IPC_CAPC1608X95N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C2AA;
Reference = C24;
ValeurCmp = 1U;
IdModule = ipc_capae:IPC_CAPAE430X540N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C2A2;
Reference = C25;
ValeurCmp = 220P;
IdModule = ipc_capc:IPC_CAPC1608X95N;
EndCmp
BeginCmp
TimeStamp = /53A9129D/53A8C71C;
Reference = C26;
ValeurCmp = 10U;
IdModule = ipc_capc:IPC_CAPC2012X140N;
EndCmp
BeginCmp
TimeStamp = /53A9129D/53AA73CE;
Reference = C27;
ValeurCmp = 100N;
IdModule = ipc_capc:IPC_CAPC1005X55N;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53A8D527;
Reference = C28;
ValeurCmp = 100N;
IdModule = ipc_capc:IPC_CAPC1005X55N;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53A8D548;
Reference = C29;
ValeurCmp = 100N;
IdModule = ipc_capc:IPC_CAPC1005X55N;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53A8D542;
Reference = C30;
ValeurCmp = 100N;
IdModule = ipc_capc:IPC_CAPC1005X55N;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53A8D54E;
Reference = C31;
ValeurCmp = 100N;
IdModule = ipc_capc:IPC_CAPC1005X55N;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53A8D5C2;
Reference = C32;
ValeurCmp = 10U;
IdModule = ipc_capc:IPC_CAPC2012X140N;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53A8D56C;
Reference = C33;
ValeurCmp = 100N;
IdModule = ipc_capc:IPC_CAPC1005X55N;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53A8D5C8;
Reference = C34;
ValeurCmp = 10U;
IdModule = ipc_capc:IPC_CAPC2012X140N;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53A8D572;
Reference = C35;
ValeurCmp = 100N;
IdModule = ipc_capc:IPC_CAPC1005X55N;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53A8D5DA;
Reference = C36;
ValeurCmp = 10U;
IdModule = ipc_capc:IPC_CAPC2012X140N;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53A8D5E0;
Reference = C37;
ValeurCmp = 10U;
IdModule = ipc_capc:IPC_CAPC2012X140N;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53A8D58C;
Reference = C38;
ValeurCmp = 10U;
IdModule = ipc_capc:IPC_CAPC2012X140N;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53A8D5AA;
Reference = C39;
ValeurCmp = DNI;
IdModule = ipc_capc:IPC_CAPC1608X90N;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53A8D592;
Reference = C40;
ValeurCmp = 10U;
IdModule = ipc_capc:IPC_CAPC2012X140N;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53A8D62C;
Reference = C41;
ValeurCmp = 10U;
IdModule = ipc_capc:IPC_CAPC2012X140N;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53B1911F;
Reference = C42;
ValeurCmp = 10U;
IdModule = ipc_capc:IPC_CAPC2012X140N;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53B1A065;
Reference = C43;
ValeurCmp = 10U;
IdModule = ipc_capc:IPC_CAPC2012X140N;
EndCmp
BeginCmp
TimeStamp = /53B309AC;
Reference = FID1;
ValeurCmp = FIDUCIAL;
IdModule = fiducial:FIDUCIAL_65MIL;
EndCmp
BeginCmp
TimeStamp = /53B30B4C;
Reference = FID2;
ValeurCmp = FIDUCIAL;
IdModule = fiducial:FIDUCIAL_65MIL;
EndCmp
BeginCmp
TimeStamp = /53B30CEC;
Reference = FID3;
ValeurCmp = FIDUCIAL;
IdModule = fiducial:FIDUCIAL_65MIL;
EndCmp
BeginCmp
TimeStamp = /53B30E8C;
Reference = FID4;
ValeurCmp = FIDUCIAL;
IdModule = fiducial:FIDUCIAL_65MIL;
EndCmp
BeginCmp
TimeStamp = /5369BBC4;
Reference = H1;
ValeurCmp = HOLE1;
IdModule = hole:HOLE_3200UM_VIAS;
EndCmp
BeginCmp
TimeStamp = /5369BBD8;
Reference = H2;
ValeurCmp = HOLE1;
IdModule = hole:HOLE_3200UM_VIAS;
EndCmp
BeginCmp
TimeStamp = /5369BBEC;
Reference = H3;
ValeurCmp = HOLE1;
IdModule = hole:HOLE_3200UM_VIAS;
EndCmp
BeginCmp
TimeStamp = /5369BC00;
Reference = H4;
ValeurCmp = HOLE1;
IdModule = hole:HOLE_3200UM_VIAS;
EndCmp
BeginCmp
TimeStamp = /5369BC14;
Reference = H5;
ValeurCmp = HOLE1;
IdModule = hole:HOLE_3200UM_VIAS;
EndCmp
BeginCmp
TimeStamp = /53A9129D/53A8C6D0;
Reference = J2;
ValeurCmp = MICROSD_DETSW;
IdModule = alps:ALPS_SCHA4B0100;
EndCmp
BeginCmp
TimeStamp = /53A9129D/53A91651;
Reference = J3;
ValeurCmp = KINGTECH_DW0240A2BZ_FPC;
IdModule = molex:MOLEX_54132-40XX_LR;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53AF093C;
Reference = L1;
ValeurCmp = L;
IdModule = ipc_indc:IPC_INDC1608X95N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53AF20F3;
Reference = L2;
ValeurCmp = L;
IdModule = ipc_indc:IPC_INDC1608X95N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53AF20FE;
Reference = L3;
ValeurCmp = L;
IdModule = ipc_indc:IPC_INDC1608X95N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C2E2;
Reference = L4;
ValeurCmp = L;
IdModule = ipc_indc:IPC_INDC1608X95N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C2E8;
Reference = L5;
ValeurCmp = L;
IdModule = ipc_indc:IPC_INDC1608X95N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C2EE;
Reference = L6;
ValeurCmp = L;
IdModule = ipc_indc:IPC_INDC1608X95N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53AF25CC;
Reference = L7;
ValeurCmp = L;
IdModule = ipc_indc:IPC_INDC1608X95N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53AF25D7;
Reference = L8;
ValeurCmp = L;
IdModule = ipc_indc:IPC_INDC1608X95N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C2F4;
Reference = L9;
ValeurCmp = L;
IdModule = ipc_indc:IPC_INDC1608X95N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53AF0931;
Reference = L10;
ValeurCmp = L;
IdModule = ipc_indc:IPC_INDC1608X95N;
EndCmp
BeginCmp
TimeStamp = /53A9129D/53A8C752;
Reference = LCD1;
ValeurCmp = KINGTECH_DW0240A2BZ_PANEL;
IdModule = lcd_kingtech:KINGTECH_DW0240A2BZ_PANEL;
EndCmp
BeginCmp
TimeStamp = /53B1AE0D;
Reference = LOGO1;
ValeurCmp = SHAREBRAINED;
IdModule = sharebrained:sharebrained_text_300;
EndCmp
BeginCmp
TimeStamp = /53B1B509;
Reference = LOGO2;
ValeurCmp = PORTAPACK_H1;
IdModule = sharebrained:portapack_text_300;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53AF0914;
Reference = P1;
ValeurCmp = TRS_JACK;
IdModule = cui:CUI_SJ-3524-SMT;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C2C6;
Reference = P2;
ValeurCmp = TRRS_SW_JACK;
IdModule = cui:CUI_SJ-43516-SMT;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53AF0926;
Reference = P3;
ValeurCmp = TRS_JACK;
IdModule = cui:CUI_SJ-3524-SMT;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53A8CDAE;
Reference = P20;
ValeurCmp = HACKRF_ONE_P20;
IdModule = header:HEADER_11X2_REV_SM_254_AP;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53A8CDB6;
Reference = P22;
ValeurCmp = HACKRF_ONE_P22;
IdModule = header:HEADER_13X2_REV_SM_254_AP;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53A8CDBE;
Reference = P28;
ValeurCmp = HACKRF_ONE_P28;
IdModule = header:HEADER_11X2_REV_SM_254_AP;
EndCmp
BeginCmp
TimeStamp = /53A9129D/53C5B6EB;
Reference = Q1;
ValeurCmp = MOSFET_N;
IdModule = ipc_sot:IPC_SOT95P230X110-3N;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53AB79CA;
Reference = R1;
ValeurCmp = 220R;
IdModule = ipc_resc:IPC_RESC1608X55N;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53AB79D5;
Reference = R2;
ValeurCmp = 220R;
IdModule = ipc_resc:IPC_RESC1608X55N;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53AB79EA;
Reference = R3;
ValeurCmp = 220R;
IdModule = ipc_resc:IPC_RESC1608X55N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53AF0B7F;
Reference = R6;
ValeurCmp = 5K6;
IdModule = ipc_resc:IPC_RESC1608X55N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53AF0B74;
Reference = R7;
ValeurCmp = 5K6;
IdModule = ipc_resc:IPC_RESC1608X55N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53AF0B8A;
Reference = R8;
ValeurCmp = 5K6;
IdModule = ipc_resc:IPC_RESC1608X55N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53AF0B95;
Reference = R9;
ValeurCmp = 5K6;
IdModule = ipc_resc:IPC_RESC1608X55N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C2B0;
Reference = R10;
ValeurCmp = 47K;
IdModule = ipc_resc:IPC_RESC1608X55N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C264;
Reference = R11;
ValeurCmp = 47K;
IdModule = ipc_resc:IPC_RESC1608X55N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C26A;
Reference = R12;
ValeurCmp = 47K;
IdModule = ipc_resc:IPC_RESC1608X55N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53AF2746;
Reference = R13;
ValeurCmp = 47K;
IdModule = ipc_resc:IPC_RESC1608X55N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53AF273B;
Reference = R14;
ValeurCmp = 47K;
IdModule = ipc_resc:IPC_RESC1608X55N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53AF2725;
Reference = R15;
ValeurCmp = 100R;
IdModule = ipc_resc:IPC_RESC1608X55N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53AF2730;
Reference = R16;
ValeurCmp = 100R;
IdModule = ipc_resc:IPC_RESC1608X55N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C296;
Reference = R17;
ValeurCmp = 47K;
IdModule = ipc_resc:IPC_RESC1608X55N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C29C;
Reference = R18;
ValeurCmp = 680R;
IdModule = ipc_resc:IPC_RESC1608X55N;
EndCmp
BeginCmp
TimeStamp = /53A9129D/53A91657;
Reference = R19;
ValeurCmp = 47K;
IdModule = ipc_resc:IPC_RESC1608X55N;
EndCmp
BeginCmp
TimeStamp = /53A9129D/53A91635;
Reference = R20;
ValeurCmp = 47K;
IdModule = ipc_resc:IPC_RESC1608X55N;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53A915E9;
Reference = R22;
ValeurCmp = 220R;
IdModule = ipc_resc:IPC_RESC1608X55N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53AB09AD;
Reference = RP1;
ValeurCmp = 220R;
IdModule = ipc_resc:IPC_RESCAXS80P160X320X60-8N;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53AB047A;
Reference = RP4;
ValeurCmp = 220R;
IdModule = ipc_resc:IPC_RESCAXS80P160X320X60-8N;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53AB04B9;
Reference = RP6;
ValeurCmp = 220R;
IdModule = ipc_resc:IPC_RESCAXS80P160X320X60-8N;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53AB04D6;
Reference = RP7;
ValeurCmp = 220R;
IdModule = ipc_resc:IPC_RESCAXS80P160X320X60-8N;
EndCmp
BeginCmp
TimeStamp = /53A9129D/53A8C6FD;
Reference = SW1;
ValeurCmp = CK_TSWB-3N-CB;
IdModule = ck:CK_TSWB-3N-CB222_LFS;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C66D;
Reference = U1;
ValeurCmp = WM8731SEDS;
IdModule = ipc_sop:IPC_SOP65P780X200-28N;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53A8D586;
Reference = U2;
ValeurCmp = REGULATOR_SOT23_5;
IdModule = ipc_sot:IPC_SOT95P280X110-5N;
EndCmp
BeginCmp
TimeStamp = /53A8C780/53A8D11B;
Reference = U3;
ValeurCmp = 5M40ZE64;
IdModule = ipc_qfp:IPC_QFP40P900X900X120-65N;
EndCmp
BeginCmp
TimeStamp = /53A8BFC3/53A8C2D6;
Reference = X1;
ValeurCmp = MIC_ELECTRET;
IdModule = cui:CUI_CMA-4544PF-W;
EndCmp
EndListe

4991
hardware/portapack_h1/portapack_h1.kicad_pcb Normal file
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1828
hardware/portapack_h1/portapack_h1.net Normal file
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BIN
hardware/portapack_h1/portapack_h1.pdf Normal file
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70
hardware/portapack_h1/portapack_h1.pro Normal file
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@ -0,0 +1,70 @@
update=Wednesday, July 15, 2015 'PMt' 10:20:27 PM
version=1
last_client=kicad
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[pcbnew/libraries]
LibDir=../../../library-kicad
LibName1=sockets
LibName2=connect
LibName3=discret
LibName4=pin_array
LibName5=divers
LibName6=smd_capacitors
LibName7=smd_resistors
LibName8=smd_crystal&oscillator
LibName9=smd_dil
LibName10=smd_transistors
LibName11=libcms
LibName12=display
LibName13=led
LibName14=dip_sockets
LibName15=pga_sockets
LibName16=valves
[general]
version=1
[eeschema]
version=1
LibDir=../../../library-kicad
[eeschema/libraries]
LibName1=hackrf_expansion
LibName2=wolfson
LibName3=passive
LibName4=lcd_kingtech
LibName5=supply
LibName6=io_expander
LibName7=trs_jack
LibName8=battery
LibName9=mosfet
LibName10=microphone
LibName11=sd
LibName12=ck
LibName13=altera
LibName14=regulator
LibName15=tp
LibName16=header
LibName17=hole
LibName18=sharebrained
LibName19=fiducial

330
hardware/portapack_h1/portapack_h1.sch Normal file
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@ -0,0 +1,330 @@
EESchema Schematic File Version 2
LIBS:hackrf_expansion
LIBS:wolfson
LIBS:passive
LIBS:lcd_kingtech
LIBS:power
LIBS:io_expander
LIBS:trs_jack
LIBS:battery
LIBS:mosfet
LIBS:microphone
LIBS:sd
LIBS:ck
LIBS:altera
LIBS:regulator
LIBS:tp
LIBS:header
LIBS:hole
LIBS:sharebrained
LIBS:fiducial
LIBS:portapack_h1-cache
EELAYER 24 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 4
Title "PortaPack H1"
Date "13 Oct 2014"
Rev "20140826"
Comp "ShareBrained Technology, Inc."
Comment1 "Copyright © 2014 Jared Boone"
Comment2 "License: GNU General Public License, version 2"
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L HOLE1 H1
U 1 1 5369BBC4
P 9500 2000
F 0 "H1" H 9500 2150 60 0000 C CNN
F 1 "HOLE1" H 9500 1850 60 0000 C CNN
F 2 "" H 9500 2000 60 0000 C CNN
F 3 "" H 9500 2000 60 0000 C CNN
1 9500 2000
1 0 0 -1
$EndComp
$Comp
L HOLE1 H2
U 1 1 5369BBD8
P 9500 2500
F 0 "H2" H 9500 2650 60 0000 C CNN
F 1 "HOLE1" H 9500 2350 60 0000 C CNN
F 2 "" H 9500 2500 60 0000 C CNN
F 3 "" H 9500 2500 60 0000 C CNN
1 9500 2500
1 0 0 -1
$EndComp
$Comp
L HOLE1 H3
U 1 1 5369BBEC
P 9500 3000
F 0 "H3" H 9500 3150 60 0000 C CNN
F 1 "HOLE1" H 9500 2850 60 0000 C CNN
F 2 "" H 9500 3000 60 0000 C CNN
F 3 "" H 9500 3000 60 0000 C CNN
1 9500 3000
1 0 0 -1
$EndComp
$Comp
L HOLE1 H4
U 1 1 5369BC00
P 9500 3500
F 0 "H4" H 9500 3650 60 0000 C CNN
F 1 "HOLE1" H 9500 3350 60 0000 C CNN
F 2 "" H 9500 3500 60 0000 C CNN
F 3 "" H 9500 3500 60 0000 C CNN
1 9500 3500
1 0 0 -1
$EndComp
$Comp
L HOLE1 H5
U 1 1 5369BC14
P 9500 4000
F 0 "H5" H 9500 4150 60 0000 C CNN
F 1 "HOLE1" H 9500 3850 60 0000 C CNN
F 2 "" H 9500 4000 60 0000 C CNN
F 3 "" H 9500 4000 60 0000 C CNN
1 9500 4000
1 0 0 -1
$EndComp
$Sheet
S 2800 1900 900 3300
U 53A8BFC3
F0 "audio" 50
F1 "audio.sch" 50
F2 "I2S0_SCK" I R 3700 2300 60
F3 "I2S0_TX_SDA" I R 3700 2500 60
F4 "I2S0_MCLK" I R 3700 2200 60
F5 "I2S0_WS" I R 3700 2400 60
F6 "SCL" I R 3700 2800 60
F7 "SDA" B R 3700 2900 60
F8 "I2S0_RX_SDA" O R 3700 2600 60
$EndSheet
Wire Wire Line
9800 2500 9700 2500
Wire Wire Line
9800 3000 9700 3000
Wire Wire Line
9800 3500 9700 3500
$Sheet
S 7600 1900 900 3300
U 53A9129D
F0 "lcd_sw_sd" 50
F1 "lcd_sw_sd.sch" 50
F2 "LCD_RS" I L 7600 2400 60
F3 "LCD_RD#" I L 7600 2500 60
F4 "LCD_WR#" I L 7600 2600 60
F5 "LCD_RESET#" I L 7600 2100 60
F6 "LCD_TE" O L 7600 3000 60
F7 "SW_SEL" O L 7600 4300 60
F8 "SW_ROT_A" O L 7600 4100 60
F9 "SW_ROT_B" O L 7600 4200 60
F10 "SW_D" O L 7600 3900 60
F11 "SW_R" O L 7600 3800 60
F12 "SW_U" O L 7600 3700 60
F13 "SW_L" O L 7600 4000 60
F14 "SD_DAT2" B L 7600 5000 60
F15 "SD_DAT3" B L 7600 5100 60
F16 "SD_CMD" B L 7600 4700 60
F17 "SD_CLK" I L 7600 4600 60
F18 "SD_DAT0" B L 7600 4800 60
F19 "SD_DAT1" B L 7600 4900 60
F20 "SD_CD" O L 7600 4500 60
F21 "TP_R" B L 7600 3300 60
F22 "TP_D" B L 7600 3400 60
F23 "TP_L" B L 7600 3500 60
F24 "TP_U" B L 7600 3200 60
F25 "LCD_DB[15..0]" B L 7600 2700 60
F26 "LCD_BACKLIGHT" I L 7600 2000 60
$EndSheet
Wire Bus Line
6600 2700 7600 2700
$Sheet
S 4700 1900 1900 3300
U 53A8C780
F0 "hackrf_if" 50
F1 "hackrf_if.sch" 50
F2 "LCD_TE" I R 6600 3000 60
F3 "SW_R" I R 6600 3800 60
F4 "SW_ROT_B" I R 6600 4200 60
F5 "SW_ROT_A" I R 6600 4100 60
F6 "SW_D" I R 6600 3900 60
F7 "SW_SEL" I R 6600 4300 60
F8 "SW_U" I R 6600 3700 60
F9 "SW_L" I R 6600 4000 60
F10 "LCD_RESET#" O R 6600 2100 60
F11 "LCD_RS" O R 6600 2400 60
F12 "LCD_RD#" O R 6600 2500 60
F13 "LCD_WR#" O R 6600 2600 60
F14 "TP_U" B R 6600 3200 60
F15 "TP_L" B R 6600 3500 60
F16 "TP_D" B R 6600 3400 60
F17 "TP_R" B R 6600 3300 60
F18 "I2S0_TX_SDA" O L 4700 2500 60
F19 "I2S0_WS" O L 4700 2400 60
F20 "I2S0_MCLK" O L 4700 2200 60
F21 "I2S0_SCK" O L 4700 2300 60
F22 "SDA" B L 4700 2900 60
F23 "SCL" O L 4700 2800 60
F24 "SD_CD" I R 6600 4500 60
F25 "SD_DAT2" B R 6600 5000 60
F26 "SD_DAT0" B R 6600 4800 60
F27 "SD_CMD" B R 6600 4700 60
F28 "SD_CLK" O R 6600 4600 60
F29 "SD_DAT3" B R 6600 5100 60
F30 "SD_DAT1" B R 6600 4900 60
F31 "I2S0_RX_SDA" I L 4700 2600 60
F32 "LCD_DB[15..0]" B R 6600 2700 60
F33 "LCD_BACKLIGHT" O R 6600 2000 60
$EndSheet
Wire Wire Line
6600 2000 7600 2000
Wire Wire Line
7600 2100 6600 2100
Wire Wire Line
7600 2400 6600 2400
Wire Wire Line
6600 2500 7600 2500
Wire Wire Line
7600 2600 6600 2600
Wire Wire Line
6600 3000 7600 3000
Wire Wire Line
7600 3200 6600 3200
Wire Wire Line
6600 3300 7600 3300
Wire Wire Line
7600 3400 6600 3400
Wire Wire Line
6600 3500 7600 3500
Wire Wire Line
6600 3700 7600 3700
Wire Wire Line
7600 3800 6600 3800
Wire Wire Line
6600 3900 7600 3900
Wire Wire Line
7600 4000 6600 4000
Wire Wire Line
6600 4100 7600 4100
Wire Wire Line
7600 4200 6600 4200
Wire Wire Line
6600 4300 7600 4300
Wire Wire Line
6600 4500 7600 4500
Wire Wire Line
6600 4600 7600 4600
Wire Wire Line
7600 4700 6600 4700
Wire Wire Line
6600 4800 7600 4800
Wire Wire Line
7600 4900 6600 4900
Wire Wire Line
6600 5000 7600 5000
Wire Wire Line
7600 5100 6600 5100
Wire Wire Line
3700 2200 4700 2200
Wire Wire Line
4700 2300 3700 2300
Wire Wire Line
3700 2400 4700 2400
Wire Wire Line
4700 2500 3700 2500
Wire Wire Line
3700 2600 4700 2600
Wire Wire Line
4700 2800 3700 2800
Wire Wire Line
3700 2900 4700 2900
Wire Wire Line
9700 2000 9800 2000
Wire Wire Line
9800 2000 9800 4100
Connection ~ 9800 2500
Connection ~ 9800 3000
Connection ~ 9800 3500
$Comp
L SHAREBRAINED LOGO1
U 1 1 53B1AE0D
P 6050 7000
F 0 "LOGO1" H 6050 7050 60 0000 C CNN
F 1 "SHAREBRAINED" H 6050 6950 60 0000 C CNN
F 2 "" H 6050 7000 60 0000 C CNN
F 3 "" H 6050 7000 60 0000 C CNN
1 6050 7000
1 0 0 -1
$EndComp
$Comp
L PORTAPACK_H1 LOGO2
U 1 1 53B1B509
P 6050 7450
F 0 "LOGO2" H 6050 7500 60 0000 C CNN
F 1 "PORTAPACK_H1" H 6050 7400 60 0000 C CNN
F 2 "" H 6050 7450 60 0000 C CNN
F 3 "" H 6050 7450 60 0000 C CNN
1 6050 7450
1 0 0 -1
$EndComp
$Comp
L FIDUCIAL FID1
U 1 1 53B309AC
P 4100 7100
F 0 "FID1" H 4100 7225 60 0000 C CNN
F 1 "FIDUCIAL" H 4100 6975 60 0000 C CNN
F 2 "" H 4100 7100 60 0000 C CNN
F 3 "" H 4100 7100 60 0000 C CNN
1 4100 7100
1 0 0 -1
$EndComp
$Comp
L FIDUCIAL FID2
U 1 1 53B30B4C
P 4100 7500
F 0 "FID2" H 4100 7625 60 0000 C CNN
F 1 "FIDUCIAL" H 4100 7375 60 0000 C CNN
F 2 "" H 4100 7500 60 0000 C CNN
F 3 "" H 4100 7500 60 0000 C CNN
1 4100 7500
1 0 0 -1
$EndComp
$Comp
L FIDUCIAL FID3
U 1 1 53B30CEC
P 4700 7100
F 0 "FID3" H 4700 7225 60 0000 C CNN
F 1 "FIDUCIAL" H 4700 6975 60 0000 C CNN
F 2 "" H 4700 7100 60 0000 C CNN
F 3 "" H 4700 7100 60 0000 C CNN
1 4700 7100
1 0 0 -1
$EndComp
$Comp
L FIDUCIAL FID4
U 1 1 53B30E8C
P 4700 7500
F 0 "FID4" H 4700 7625 60 0000 C CNN
F 1 "FIDUCIAL" H 4700 7375 60 0000 C CNN
F 2 "" H 4700 7500 60 0000 C CNN
F 3 "" H 4700 7500 60 0000 C CNN
1 4700 7500
1 0 0 -1
$EndComp
$Comp
L GND #PWR01
U 1 1 53B3303D
P 9800 4100
F 0 "#PWR01" H 9800 4100 30 0001 C CNN
F 1 "GND" H 9800 4030 30 0001 C CNN
F 2 "" H 9800 4100 60 0000 C CNN
F 3 "" H 9800 4100 60 0000 C CNN
1 9800 4100
1 0 0 -1
$EndComp
Wire Wire Line
9700 4000 9800 4000
Connection ~ 9800 4000
$EndSCHEMATC