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279
bertos/cpu/frame.h
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279
bertos/cpu/frame.h
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/**
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* \file
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* <!--
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* This file is part of BeRTOS.
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*
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* Bertos is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* As a special exception, you may use this file as part of a free software
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* library without restriction. Specifically, if other files instantiate
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* templates or use macros or inline functions from this file, or you compile
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* this file and link it with other files to produce an executable, this
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* file does not by itself cause the resulting executable to be covered by
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* the GNU General Public License. This exception does not however
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* invalidate any other reasons why the executable file might be covered by
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* the GNU General Public License.
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*
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* Copyright 2008 Bernie Innocenti <bernie@codewiz.org>
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* Copyright 2004, 2005, 2006, 2007, 2008 Develer S.r.l. (http://www.develer.com/)
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* Copyright 2004 Giovanni Bajo
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*
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* -->
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*
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* \brief CPU-specific stack frame handling macros.
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*
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* These are mainly used by the portable part of the scheduler
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* to work with the process stack frames.
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*
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* \author Giovanni Bajo <rasky@develer.com>
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* \author Bernie Innocenti <bernie@codewiz.org>
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* \author Stefano Fedrigo <aleph@develer.com>
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* \author Francesco Sacchi <batt@develer.com>
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*/
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#ifndef CPU_FRAME_H
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#define CPU_FRAME_H
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#include <cpu/detect.h>
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#include "cfg/cfg_arch.h" /* ARCH_EMUL */
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#include <cfg/compiler.h> /* for uintXX_t */
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#if CPU_X86
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#if CPU_X86_32
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#define CPU_SAVED_REGS_CNT 2
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#elif CPU_X86_64
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#define CPU_SAVED_REGS_CNT 8
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#else
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#error "unknown CPU"
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#endif
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#define CPU_STACK_GROWS_UPWARD 0
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#define CPU_SP_ON_EMPTY_SLOT 0
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#elif CPU_ARM
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#define CPU_SAVED_REGS_CNT 8
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#define CPU_STACK_GROWS_UPWARD 0
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#define CPU_SP_ON_EMPTY_SLOT 0
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#elif CPU_CM3
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#define CPU_SAVED_REGS_CNT 8
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#define CPU_STACK_GROWS_UPWARD 0
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#define CPU_SP_ON_EMPTY_SLOT 0
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#elif CPU_PPC
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#define CPU_SAVED_REGS_CNT 1
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#define CPU_STACK_GROWS_UPWARD 0
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#define CPU_SP_ON_EMPTY_SLOT 1
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#elif CPU_DSP56K
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#define CPU_SAVED_REGS_CNT 8
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#define CPU_STACK_GROWS_UPWARD 1
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#define CPU_SP_ON_EMPTY_SLOT 0
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#elif CPU_AVR
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#define CPU_SAVED_REGS_CNT 18
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#define CPU_STACK_GROWS_UPWARD 0
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#define CPU_SP_ON_EMPTY_SLOT 1
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#elif CPU_MSP430
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#define CPU_SAVED_REGS_CNT 16
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#define CPU_STACK_GROWS_UPWARD 1
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#define CPU_SP_ON_EMPTY_SLOT 0
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#else
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#error No CPU_... defined.
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#endif
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#ifndef CPU_STACK_GROWS_UPWARD
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#error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
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#endif
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#ifndef CPU_SP_ON_EMPTY_SLOT
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#error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
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#endif
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/// Default for macro not defined in the right arch section
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#ifndef CPU_REG_INIT_VALUE
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#define CPU_REG_INIT_VALUE(reg) (reg)
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#endif
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/*
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* Support stack handling peculiarities of a few CPUs.
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*
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* Most processors let their stack grow downward and
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* keep SP pointing at the last pushed value.
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*/
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#if !CPU_STACK_GROWS_UPWARD
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#if !CPU_SP_ON_EMPTY_SLOT
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/* Most microprocessors (x86, m68k...) */
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#define CPU_PUSH_WORD(sp, data) \
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do { *--(sp) = (data); } while (0)
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#define CPU_POP_WORD(sp) \
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(*(sp)++)
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#else
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/* AVR insanity */
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#define CPU_PUSH_WORD(sp, data) \
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do { *(sp)-- = (data); } while (0)
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#define CPU_POP_WORD(sp) \
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(*++(sp))
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#endif
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#else /* CPU_STACK_GROWS_UPWARD */
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#if !CPU_SP_ON_EMPTY_SLOT
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/* DSP56K and other weirdos */
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#define CPU_PUSH_WORD(sp, data) \
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do { *++(sp) = (cpu_stack_t)(data); } while (0)
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#define CPU_POP_WORD(sp) \
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(*(sp)--)
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#else
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#error I bet you cannot find a CPU like this
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#endif
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#endif
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#if CPU_DSP56K
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/*
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* DSP56k pushes both PC and SR to the stack in the JSR instruction, but
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* RTS discards SR while returning (it does not restore it). So we push
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* 0 to fake the same context.
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*/
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#define CPU_PUSH_CALL_FRAME(sp, func) \
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do { \
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CPU_PUSH_WORD((sp), (func)); \
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CPU_PUSH_WORD((sp), 0x100); \
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} while (0);
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#elif CPU_CM3
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#if CONFIG_KERN_PREEMPT
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INLINE void cm3_preempt_switch_context(cpu_stack_t **new_sp, cpu_stack_t **old_sp)
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{
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register cpu_stack_t **__new_sp asm ("r0") = new_sp;
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register cpu_stack_t **__old_sp asm ("r1") = old_sp;
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asm volatile ("svc #0"
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: : "r"(__new_sp), "r"(__old_sp) : "memory", "cc");
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}
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#define asm_switch_context cm3_preempt_switch_context
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#define CPU_CREATE_NEW_STACK(stack) \
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do { \
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size_t i; \
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/* Initialize process stack frame */ \
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CPU_PUSH_WORD((stack), 0x01000000); /* xPSR */ \
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CPU_PUSH_WORD((stack), (cpu_stack_t)proc_entry); /* pc */ \
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CPU_PUSH_WORD((stack), 0); /* lr */ \
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CPU_PUSH_WORD((stack), 0); /* ip */ \
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CPU_PUSH_WORD((stack), 0); /* r3 */ \
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CPU_PUSH_WORD((stack), 0); /* r2 */ \
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CPU_PUSH_WORD((stack), 0); /* r1 */ \
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CPU_PUSH_WORD((stack), 0); /* r0 */ \
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CPU_PUSH_WORD((stack), 0xfffffffd); /* lr_exc */ \
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/* Push a clean set of CPU registers for asm_switch_context() */ \
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for (i = 0; i < CPU_SAVED_REGS_CNT; i++) \
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CPU_PUSH_WORD(stack, CPU_REG_INIT_VALUE(i)); \
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CPU_PUSH_WORD(stack, IRQ_PRIO_DISABLED); \
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} while (0)
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#endif /* CONFIG_KERN_PREEMPT */
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#elif CPU_AVR
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/*
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* On AVR, addresses are pushed into the stack as little-endian, while
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* memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
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* no natural endianess).
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*/
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#define CPU_PUSH_CALL_FRAME(sp, func) \
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do { \
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uint16_t funcaddr = (uint16_t)(func); \
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CPU_PUSH_WORD((sp), funcaddr); \
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CPU_PUSH_WORD((sp), funcaddr>>8); \
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} while (0)
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/*
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* If the kernel is in idle-spinning, the processor executes:
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*
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* IRQ_ENABLE;
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* CPU_IDLE;
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* IRQ_DISABLE;
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*
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* IRQ_ENABLE is translated in asm as "sei" and IRQ_DISABLE as "cli".
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* We could define CPU_IDLE to expand to none, so the resulting
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* asm code would be:
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*
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* sei;
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* cli;
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*
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* But Atmel datasheet states:
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* "When using the SEI instruction to enable interrupts,
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* the instruction following SEI will be executed *before*
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* any pending interrupts", so "cli" is executed before any
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* pending interrupt with the result that IRQs will *NOT*
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* be enabled!
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* To ensure that IRQ will run a NOP is required.
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*/
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#define CPU_IDLE NOP
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#elif CPU_PPC
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#define CPU_PUSH_CALL_FRAME(sp, func) \
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do { \
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CPU_PUSH_WORD((sp), (cpu_stack_t)(func)); /* LR -> 8(SP) */ \
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CPU_PUSH_WORD((sp), 0); /* CR -> 4(SP) */ \
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} while (0)
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#endif
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#ifndef CPU_PUSH_CALL_FRAME
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#define CPU_PUSH_CALL_FRAME(sp, func) \
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CPU_PUSH_WORD((sp), (cpu_stack_t)(func))
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#endif
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/**
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* \def CPU_IDLE
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*
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* \brief Invoked by the scheduler to stop the CPU when idle.
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*
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* This hook can be redefined to put the CPU in low-power mode, or to
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* profile system load with an external strobe, or to save CPU cycles
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* in hosted environments such as emulators.
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*/
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#ifndef CPU_IDLE
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#define CPU_IDLE PAUSE
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#endif /* !CPU_IDLE */
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/**
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* Default macro for creating a new Process stack
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*/
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#ifndef CPU_CREATE_NEW_STACK
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#define CPU_CREATE_NEW_STACK(stack) \
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do { \
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size_t i; \
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/* Initialize process stack frame */ \
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CPU_PUSH_CALL_FRAME(stack, proc_entry); \
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/* Push a clean set of CPU registers for asm_switch_context() */ \
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for (i = 0; i < CPU_SAVED_REGS_CNT; i++) \
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CPU_PUSH_WORD(stack, CPU_REG_INIT_VALUE(i)); \
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} while (0)
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#endif
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#endif /* CPU_ATTR_H */
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