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257
bertos/cpu/avr/drv/timer_mega.c
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257
bertos/cpu/avr/drv/timer_mega.c
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/**
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* \file
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* <!--
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* This file is part of BeRTOS.
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*
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* Bertos is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* As a special exception, you may use this file as part of a free software
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* library without restriction. Specifically, if other files instantiate
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* templates or use macros or inline functions from this file, or you compile
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* this file and link it with other files to produce an executable, this
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* file does not by itself cause the resulting executable to be covered by
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* the GNU General Public License. This exception does not however
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* invalidate any other reasons why the executable file might be covered by
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* the GNU General Public License.
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*
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* Copyright 2005, 2010 Develer S.r.l. (http://www.develer.com/)
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*
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* -->
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*
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* \author Bernie Innocenti <bernie@codewiz.org>
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* \author Francesco Sacchi <batt@develer.com>
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* \author Luca Ottaviano <lottaviano@develer.com>
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*
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* \brief Low-level timer module for AVR MEGA (implementation).
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*
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* This module is automatically included so no need to include
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* in test list.
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* notest: avr
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*/
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#include <drv/timer_mega.h>
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#include <cfg/macros.h> // BV()
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#include <cpu/types.h>
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#include <cpu/irq.h>
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#include <avr/io.h>
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#if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P || CPU_AVR_ATMEGA2560
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#define REG_TIFR0 TIFR0
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#define REG_TIFR1 TIFR1
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#define REG_TIFR2 TIFR2
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#if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
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#define REG_TIFR3 TIFR3
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#endif
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#define REG_TIMSK0 TIMSK0
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#define REG_TIMSK1 TIMSK1
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#define REG_TIMSK2 TIMSK2
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#if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
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#define REG_TIMSK3 TIMSK3
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#endif
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#define REG_TCCR0A TCCR0A
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#define REG_TCCR0B TCCR0B
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#define REG_TCCR2A TCCR2A
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#define REG_TCCR2B TCCR2B
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#define REG_OCR0A OCR0A
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#define REG_OCR2A OCR2A
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#define BIT_OCF0A OCF0A
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#define BIT_OCF2A OCF2A
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#define BIT_OCIE0A OCIE0A
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#define BIT_OCIE2A OCIE2A
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#else
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#define REG_TIFR0 TIFR
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#define REG_TIFR1 TIFR
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#define REG_TIFR2 TIFR
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#define REG_TIFR3 TIFR
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#define REG_TIMSK0 TIMSK
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#define REG_TIMSK1 TIMSK
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#define REG_TIMSK2 TIMSK
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#define REG_TIMSK3 ETIMSK
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#define REG_TCCR0A TCCR0
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#define REG_TCCR0B TCCR0
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#define REG_TCCR2A TCCR2
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#define REG_TCCR2B TCCR2
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#define REG_OCR0A OCR0
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#define REG_OCR2A OCR2
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#define BIT_OCF0A OCF0
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#define BIT_OCF2A OCF2
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#define BIT_OCIE0A OCIE0
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#define BIT_OCIE2A OCIE2
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#endif
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#if CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA103
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/* These ATMega have different prescaler options. */
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#define TIMER0_PRESCALER_64 BV(CS02)
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#define TIMER2_PRESCALER_64 (BV(CS21) | BV(CS20))
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#else
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#define TIMER0_PRESCALER_64 (BV(CS01) | BV(CS00))
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#define TIMER2_PRESCALER_64 BV(CS22)
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#endif
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/** HW dependent timer initialization */
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#if (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0)
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void timer_hw_init(void)
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{
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cpu_flags_t flags;
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IRQ_SAVE_DISABLE(flags);
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/* Reset Timer flags */
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REG_TIFR0 = BV(BIT_OCF0A) | BV(TOV0);
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/* Setup Timer/Counter interrupt */
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REG_TCCR0A = 0; // TCCR2 reg could be separate or a unique register with both A & B values, this is needed to
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REG_TCCR0B = 0;
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REG_TCCR0A = BV(WGM01); /* Clear on Compare match */
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#if TIMER_PRESCALER == 64
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REG_TCCR0B |= TIMER0_PRESCALER_64;
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#else
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#error Unsupported value of TIMER_PRESCALER
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#endif
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TCNT0 = 0x00; /* Initialization of Timer/Counter */
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REG_OCR0A = OCR_DIVISOR; /* Timer/Counter Output Compare Register */
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/* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */
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REG_TIMSK0 &= ~BV(TOIE0);
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REG_TIMSK0 |= BV(BIT_OCIE0A);
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IRQ_RESTORE(flags);
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}
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#elif (CONFIG_TIMER == TIMER_ON_OVERFLOW1)
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void timer_hw_init(void)
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{
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cpu_flags_t flags;
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IRQ_SAVE_DISABLE(flags);
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/* Reset Timer overflow flag */
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REG_TIFR1 |= BV(TOV1);
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/* Fast PWM mode, 9 bit, 24 kHz, no prescaling. */
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#if (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 9)
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TCCR1A |= BV(WGM11);
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TCCR1A &= ~BV(WGM10);
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TCCR1B |= BV(WGM12) | BV(CS10);
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TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12));
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/* Fast PWM mode, 8 bit, 24 kHz, no prescaling. */
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#elif (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 8)
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TCCR1A |= BV(WGM10);
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TCCR1A &= ~BV(WGM11);
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TCCR1B |= BV(WGM12) | BV(CS10);
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TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12));
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#else
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#error Unsupported value of TIMER_PRESCALER or TIMER_HW_BITS
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#endif
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TCNT1 = 0x00; /* initialization of Timer/Counter */
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/* Enable timer interrupt: Timer/Counter1 Overflow */
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REG_TIMSK1 |= BV(TOIE1);
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IRQ_RESTORE(flags);
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}
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#elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2)
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void timer_hw_init(void)
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{
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cpu_flags_t flags;
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IRQ_SAVE_DISABLE(flags);
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/* Reset Timer flags */
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REG_TIFR2 = BV(BIT_OCF2A) | BV(TOV2);
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/* Setup Timer/Counter interrupt */
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REG_TCCR2A = 0; // TCCR2 reg could be separate or a unique register with both A & B values, this is needed to
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REG_TCCR2B = 0; // ensure correct initialization.
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REG_TCCR2A = BV(WGM21);
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#if TIMER_PRESCALER == 64
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REG_TCCR2B |= TIMER2_PRESCALER_64;
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#else
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#error Unsupported value of TIMER_PRESCALER
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#endif
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/* Clear on Compare match & prescaler = 64, internal sys clock.
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When changing prescaler change TIMER_HW_HPTICKS_PER_SEC too */
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TCNT2 = 0x00; /* initialization of Timer/Counter */
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REG_OCR2A = (uint8_t)OCR_DIVISOR; /* Timer/Counter Output Compare Register */
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/* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */
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REG_TIMSK2 &= ~BV(TOIE2);
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REG_TIMSK2 |= BV(BIT_OCIE2A);
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IRQ_RESTORE(flags);
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}
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#elif (CONFIG_TIMER == TIMER_ON_OVERFLOW3)
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#if CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P || CPU_AVR_ATMEGA32
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#error For select target there is not TIMER_ON_OVERFLOW3, please select an other one.
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#endif
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void timer_hw_init(void)
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{
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cpu_flags_t flags;
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IRQ_SAVE_DISABLE(flags);
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/* Reset Timer overflow flag */
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REG_TIFR3 |= BV(TOV3);
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/* Fast PWM mode, 9 bit, 24 kHz, no prescaling. */
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#if (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 9)
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TCCR3A |= BV(WGM31);
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TCCR3A &= ~BV(WGM30);
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TCCR3B |= BV(WGM32) | BV(CS30);
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TCCR3B &= ~(BV(WGM33) | BV(CS31) | BV(CS32));
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/* Fast PWM mode, 8 bit, 24 kHz, no prescaling. */
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#elif (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 8)
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TCCR3A |= BV(WGM30);
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TCCR3A &= ~BV(WGM31);
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TCCR3B |= BV(WGM32) | BV(CS30);
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TCCR3B &= ~(BV(WGM33) | BV(CS31) | BV(CS32));
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#else
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#error Unsupported value of TIMER_PRESCALER or TIMER_HW_BITS
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#endif
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/* initialization of Timer/Counter */
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TCNT3 = 0x00;
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/* Enable timer interrupt: Timer/Counter3 Overflow */
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REG_TIMSK3 |= BV(TOIE3);
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IRQ_RESTORE(flags);
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}
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#else
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#error Unimplemented value for CONFIG_TIMER
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#endif /* CONFIG_TIMER */
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