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bertos/cpu/arm/io/at91_aic.h
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222
bertos/cpu/arm/io/at91_aic.h
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/**
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* \file
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* <!--
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* This file is part of BeRTOS.
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*
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* Bertos is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* As a special exception, you may use this file as part of a free software
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* library without restriction. Specifically, if other files instantiate
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* templates or use macros or inline functions from this file, or you compile
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* this file and link it with other files to produce an executable, this
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* file does not by itself cause the resulting executable to be covered by
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* the GNU General Public License. This exception does not however
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* invalidate any other reasons why the executable file might be covered by
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* the GNU General Public License.
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*
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* Copyright 2007 Develer S.r.l. (http://www.develer.com/)
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*
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* -->
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*
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*
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* \author Francesco Sacchi <batt@develer.com>
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*
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* AT91 advanced interrupt controller.
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* This file is based on NUT/OS implementation. See license below.
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*/
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/*
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* Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the copyright holders nor the names of
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
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* SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* For additional information see http://www.ethernut.de/
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*/
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#ifndef AT91_AIC_H
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#define AT91_AIC_H
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#include <cfg/compiler.h>
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/**
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* Source mode register array.
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*/
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#define AIC_SMR(i) (*((reg32_t *)(AIC_BASE + (i) * 4)))
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/**
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* Priority mask.
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* Priority levels can be between 0 (lowest) and 7 (highest).
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*/
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#define AIC_PRIOR_MASK 0x00000007
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/**
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* Interrupt source type mask.
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* Internal interrupts can level sensitive or edge triggered.
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*
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* External interrupts can triggered on positive or negative levels or
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* on rising or falling edges.
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*/
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/*\{*/
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#define AIC_SRCTYPE_MASK 0x00000060
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#define AIC_SRCTYPE_INT_LEVEL_SENSITIVE 0x00000000 ///< Internal level sensitive.
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#define AIC_SRCTYPE_INT_EDGE_TRIGGERED 0x00000020 ///< Internal edge triggered.
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#define AIC_SRCTYPE_EXT_LOW_LEVEL 0x00000000 ///< External low level.
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#define AIC_SRCTYPE_EXT_NEGATIVE_EDGE 0x00000020 ///< External falling edge.
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#define AIC_SRCTYPE_EXT_HIGH_LEVEL 0x00000040 ///< External high level.
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#define AIC_SRCTYPE_EXT_POSITIVE_EDGE 0x00000060 ///< External rising edge.
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/*\}*/
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/**
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* Type for interrupt handlers.
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*/
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typedef void (*irq_handler_t)(void);
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/** Interrupt Source Vector Registers */
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/*\{*/
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/** Source vector register array.
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*
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* Stores the addresses of the corresponding interrupt handlers.
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*/
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#define AIC_SVR(i) (*((volatile irq_handler_t *)(AIC_BASE + 0x80 + (i) * 4)))
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/*\}*/
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/** Interrupt Vector Register */
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/*\{*/
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#define AIC_IVR_OFF 0x00000100 ///< IRQ vector register offset.
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#define AIC_IVR (*((reg32_t *)(AIC_BASE + AIC_IVR_OFF))) ///< IRQ vector register address.
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/*\}*/
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/** Fast Interrupt Vector Register */
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/*\{*/
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#define AIC_FVR_OFF 0x00000104 ///< FIQ vector register offset.
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#define AIC_FVR (*((reg32_t *)(AIC_BASE + AIC_FVR_OFF))) ///< FIQ vector register address.
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/*\}*/
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/** Interrupt Status Register */
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/*\{*/
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#define AIC_ISR_OFF 0x00000108 ///< Interrupt status register offset.
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#define AIC_ISR (*((reg32_t *)(AIC_BASE + AIC_ISR_OFF))) ///< Interrupt status register address.
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#define AIC_IRQID_MASK 0x0000001F ///< Current interrupt identifier mask.
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/*\}*/
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/** Interrupt Pending Register */
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/*\{*/
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#define AIC_IPR_OFF 0x0000010C ///< Interrupt pending register offset.
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#define AIC_IPR (*((reg32_t *)(AIC_BASE + AIC_IPR_OFF))) ///< Interrupt pending register address.
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/*\}*/
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/** Interrupt Mask Register */
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/*\{*/
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#define AIC_IMR_OFF 0x00000110 ///< Interrupt mask register offset.
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#define AIC_IMR (*((reg32_t *)(AIC_BASE + AIC_IMR_OFF))) ///< Interrupt mask register address.
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/*\}*/
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/** Interrupt Core Status Register */
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/*\{*/
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#define AIC_CISR_OFF 0x00000114 ///< Core interrupt status register offset.
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#define AIC_CISR (*((reg32_t *)(AIC_BASE + AIC_CISR_OFF))) ///< Core interrupt status register address.
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#define AIC_NFIQ 1 ///< Core FIQ Status
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#define AIC_NIRQ 2 ///< Core IRQ Status
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/*\}*/
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/** Interrupt Enable Command Register */
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/*\{*/
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#define AIC_IECR_OFF 0x00000120 ///< Interrupt enable command register offset.
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#define AIC_IECR (*((reg32_t *)(AIC_BASE + AIC_IECR_OFF))) ///< Interrupt enable command register address.
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/*\}*/
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/** Interrupt Disable Command Register */
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/*\{*/
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#define AIC_IDCR_OFF 0x00000124 ///< Interrupt disable command register offset.
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#define AIC_IDCR (*((reg32_t *)(AIC_BASE + AIC_IDCR_OFF))) ///< Interrupt disable command register address.
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/*\}*/
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/** Interrupt Clear Command Register */
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/*\{*/
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#define AIC_ICCR_OFF 0x00000128 ///< Interrupt clear command register offset.
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#define AIC_ICCR (*((reg32_t *)(AIC_BASE + AIC_ICCR_OFF))) ///< Interrupt clear command register address.
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/*\}*/
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/** Interrupt Set Command Register */
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/*\{*/
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#define AIC_ISCR_OFF 0x0000012C ///< Interrupt set command register offset.
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#define AIC_ISCR (*((reg32_t *)(AIC_BASE + AIC_ISCR_OFF))) ///< Interrupt set command register address.
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/*\}*/
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/** End Of Interrupt Command Register */
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/*\{*/
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#define AIC_EOICR_OFF 0x00000130 ///< End of interrupt command register offset.
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#define AIC_EOICR (*((reg32_t *)(AIC_BASE + AIC_EOICR_OFF))) ///< End of interrupt command register address.
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/*\}*/
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/** Spurious Interrupt Vector Register */
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/*\{*/
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#define AIC_SPU_OFF 0x00000134 ///< Spurious vector register offset.
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#define AIC_SPU (*((reg32_t *)(AIC_BASE + AIC_SPU_OFF)== ///< Spurious vector register address.
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/*\}*/
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/** Debug Control Register */
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/*\{*/
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#define AIC_DCR_OFF 0x0000138 ///< Debug control register offset.
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#define AIC_DCR (*((reg32_t *)(AIC_BASE + AIC_DCR_OFF))) ///< Debug control register address.
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/*\}*/
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/** Fast Forcing Enable Register */
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/*\{*/
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#define AIC_FFER_OFF 0x00000140 ///< Fast forcing enable register offset.
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#define AIC_FFER (*((reg32_t *)(AIC_BASE + AIC_FFER_OFF))) ///< Fast forcing enable register address.
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/*\}*/
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/** Fast Forcing Disable Register */
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/*\{*/
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#define AIC_FFDR_OFF 0x00000144 ///< Fast forcing disable register address.
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#define AIC_FFDR (*((reg32_t *)(AIC_BASE + AIC_FFDR_OFF))) ///< Fast forcing disable register address.
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/*\}*/
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/** Fast Forcing Status Register */
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/*\{*/
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#define AIC_FFSR_OFF 0x00000148 ///< Fast forcing status register address.
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#define AIC_FFSR (*((reg32_t *)(AIC_BASE + AIC_FFSR_OFF))) ///< Fast forcing status register address.
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/*\}*/
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#endif /* AT91_AIC_H */
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