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55
bertos/cpu/arm/io/arm.h Normal file
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/**
* \file
* <!--
* This file is part of BeRTOS.
*
* Bertos is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* As a special exception, you may use this file as part of a free software
* library without restriction. Specifically, if other files instantiate
* templates or use macros or inline functions from this file, or you compile
* this file and link it with other files to produce an executable, this
* file does not by itself cause the resulting executable to be covered by
* the GNU General Public License. This exception does not however
* invalidate any other reasons why the executable file might be covered by
* the GNU General Public License.
*
* Copyright 2007 Develer S.r.l. (http://www.develer.com/)
*
* -->
*
*
* \author Francesco Sacchi <batt@develer.com>
*
* ARM I/O registers.
*/
#ifndef ARM_H
#define ARM_H
#include <cpu/detect.h>
#if CPU_ARM_AT91
#include "at91.h"
#elif CPU_ARM_LPC2
#include "lpc23xx.h"
/*#elif Add other ARM families here */
#else
#error Unknown CPU
#endif
#endif /* ARM_H */

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/**
* \file
* <!--
* This file is part of BeRTOS.
*
* Bertos is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* As a special exception, you may use this file as part of a free software
* library without restriction. Specifically, if other files instantiate
* templates or use macros or inline functions from this file, or you compile
* this file and link it with other files to produce an executable, this
* file does not by itself cause the resulting executable to be covered by
* the GNU General Public License. This exception does not however
* invalidate any other reasons why the executable file might be covered by
* the GNU General Public License.
*
* Copyright 2007 Develer S.r.l. (http://www.develer.com/)
*
* -->
*
*
* \author Francesco Sacchi <batt@develer.com>
*
* AT91 common definitions.
* This file is based on NUT/OS implementation. See license below.
*/
/*
* Copyright (C) 2006-2007 by egnite Software GmbH. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
* SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* For additional information see http://www.ethernut.de/
*/
#ifndef AT91_H
#define AT91_H
#include <cpu/detect.h>
#if CPU_ARM_SAM7S_LARGE || CPU_ARM_SAM7X
#include "at91sam7.h"
#else
#error Missing I/O definitions for CPU.
#endif
#endif /* AT91_H */

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/**
* \file
* <!--
* This file is part of BeRTOS.
*
* Bertos is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* As a special exception, you may use this file as part of a free software
* library without restriction. Specifically, if other files instantiate
* templates or use macros or inline functions from this file, or you compile
* this file and link it with other files to produce an executable, this
* file does not by itself cause the resulting executable to be covered by
* the GNU General Public License. This exception does not however
* invalidate any other reasons why the executable file might be covered by
* the GNU General Public License.
*
* Copyright 2007 Develer S.r.l. (http://www.develer.com/)
*
* -->
*
* \author Daniele Basile <asterix@develer.com>
*
* AT91SAM7 Analog to Digital Converter.
*
*/
#ifndef AT91_ADC_H
#define AT91_ADC_H
/**
* ADC control register
*/
#define ADC_CR_OFF 0x00000000 ///< Control register offeset.
#define ADC_CR (*((reg32_t *)(ADC_BASE + ADC_CR_OFF))) ///< Control register address.
#define ADC_SWRST 0 ///< Software reset.
#define ADC_START 1 ///< Start conversion.
/**
* ADC mode register
*/
#define ADC_MR_OFF 0x00000004 ///< Mode register offeset.
#define ADC_MR (*((reg32_t *)(ADC_BASE + ADC_MR_OFF))) ///< Mode register address.
#define ADC_TRGEN 0 ///< Trigger enable.
#define ADC_TRGSEL_TIOA0 0x00000000 ///< TIOA output of the timer counter channel 0.
#define ADC_TRGSEL_TIOA1 0x00000002 ///< TIOA output of the timer counter channel 1.
#define ADC_TRGSEL_TIOA2 0x00000004 ///< TIOA output of the timer counter channel 2.
#define ADC_TRGSEL_EXT 0x0000000C ///< External trigger.
#define ADC_LOWRES 4 ///< Resolution 0: 10-bit, 1: 8-bit.
#define ADC_SLEEP 5 ///< Sleep mode.
/**
* Prescaler rate selection.
* ADCClock = MCK / ((ADC_PRESCALER_VALUE + 1) * 2)
*/
#define ADC_PRESCALER_MASK 0x00003F00 ///< Prescaler rate selection mask.
#define ADC_PRESCALER_SHIFT 8 ///< Prescale rate selection shift.
/**
* Start up timer.
* Startup time = (ADC_STARTUP_VALUE + 1) * 8 /ADCClock
*/
#define ADC_STARTUP_MASK 0x001F0000 ///< Start up timer mask.
#define ADC_STARTUP_SHIFT 16 ///< Start up timer shift.
/**
* Sample & hold time.
* Sample & hold time = (ADC_SHTIM_VALUE + 1) * 8 /ADCClock
*/
#define ADC_SHTIME_MASK 0x0F000000 ///< Sample & hold time mask.
#define ADC_SHTIME_SHIFT 24 ///< Sample & hold time shift.
/**
* ADC channel enable register
*/
#define ADC_CHER_OFF 0x00000010 ///< Channel enable register offeset.
#define ADC_CHER (*((reg32_t *)(ADC_BASE + ADC_CHER_OFF))) ///< Channel enable register address.
/**
* ADC channel disable register
*/
#define ADC_CHDR_OFF 0x00000014 ///< Channel disable register offeset.
#define ADC_CHDR (*((reg32_t *)(ADC_BASE + ADC_CHDR_OFF))) ///< Channel disable register address.
/**
* ADC channel status register
*/
#define ADC_CHSR_OFF 0x00000018 ///< Channel status register offeset.
#define ADC_CHSR (*((reg32_t *)(ADC_BASE + ADC_CHSR_OFF))) ///< Channel status register address.
#define ADC_CH_MASK 0x000000FF ///< Channel mask.
#define ADC_CH0 0 ///< Channel 0
#define ADC_CH1 1 ///< Channel 1
#define ADC_CH2 2 ///< Channel 2
#define ADC_CH3 3 ///< Channel 3
#define ADC_CH4 4 ///< Channel 4
#define ADC_CH5 5 ///< Channel 5
#define ADC_CH6 6 ///< Channel 6
#define ADC_CH7 7 ///< Channel 7
/**
* ADC status register
*/
#define ADC_SR_OFF 0x0000001C ///< Status register offeset.
#define ADC_SR (*((reg32_t *)(ADC_BASE + ADC_SR_OFF))) ///< Status register address.
/**
* ADC Interrupt enable register.
*/
#define ADC_IER_OFF 0x00000024 ///< Interrupt enable register offeset.
#define ADC_IER (*((reg32_t *)(ADC_BASE + ADC_IER_OFF))) ///< Interrupt enable register.
/**
* ADC Interrupt disable register.
*/
#define ADC_IDR_OFF 0x00000028 ///< Interrupt disable register offeset.
#define ADC_IDR (*((reg32_t *)(ADC_BASE + ADC_IDR_OFF))) ///< Interrupt disable register.
/**
* ADC Interrupt mask register.
*/
#define ADC_IMR_OFF 0x0000002C ///< Interrupt mask register offeset.
#define ADC_IMR (*((reg32_t *)(ADC_BASE + ADC_IMR_OFF))) ///< Interrupt mask register.
#define ADC_EOC_MASK 0x000000FF ///< End of converison mask.
#define ADC_EOC0 0 ///< End of conversion channel 0.
#define ADC_EOC1 1 ///< End of conversion channel 1.
#define ADC_EOC2 2 ///< End of conversion channel 2.
#define ADC_EOC3 3 ///< End of conversion channel 3.
#define ADC_EOC4 4 ///< End of conversion channel 4.
#define ADC_EOC5 5 ///< End of conversion channel 5.
#define ADC_EOC6 6 ///< End of conversion channel 6.
#define ADC_EOC7 7 ///< End of conversion channel 7.
#define ADC_OVRE0 8 ///< Overrun error channel 0.
#define ADC_OVRE1 9 ///< Overrun error channel 1.
#define ADC_OVRE2 10 ///< Overrun error channel 2.
#define ADC_OVRE3 11 ///< Overrun error channel 3.
#define ADC_OVRE4 12 ///< Overrun error channel 4.
#define ADC_OVRE5 13 ///< Overrun error channel 5.
#define ADC_OVRE6 14 ///< Overrun error channel 6.
#define ADC_OVRE7 15 ///< Overrun error channel 7.
#define ADC_DRDY 16 ///< Data ready.
#define ADC_GOVRE 17 ///< General overrun error.
#define ADC_ENDRX 18 ///< End of RX buffer.
#define ADC_RXBUFF 19 ///< Rx buffer full.
/**
* ADC last convert data register.
*/
#define ADC_LCDR_OFF 0x00000020 ///< Last converted data register offeset.
#define ADC_LCDR (*((reg32_t *)(ADC_BASE + ADC_LCDR_OFF))) ///< Last converted data register.
/**
* ADC channel data register.
*
* \{
*/
#define ADC_CDR0_OFF 0x00000030 ///< Channel data register 0 offeset.
#define ADC_CDR1_OFF 0x00000034 ///< Channel data register 1 offeset.
#define ADC_CDR2_OFF 0x00000038 ///< Channel data register 2 offeset.
#define ADC_CDR3_OFF 0x0000003C ///< Channel data register 3 offeset.
#define ADC_CDR4_OFF 0x00000040 ///< Channel data register 4 offeset.
#define ADC_CDR5_OFF 0x00000044 ///< Channel data register 5 offeset.
#define ADC_CDR6_OFF 0x00000048 ///< Channel data register 6 offeset.
#define ADC_CDR7_OFF 0x0000004C ///< Channel data register 7 offeset.
#define ADC_CDR0 (*((reg32_t *)(ADC_BASE + ADC_CDR0_OFF))) ///< Channel data register 0.
#define ADC_CDR1 (*((reg32_t *)(ADC_BASE + ADC_CDR1_OFF))) ///< Channel data register 1.
#define ADC_CDR2 (*((reg32_t *)(ADC_BASE + ADC_CDR2_OFF))) ///< Channel data register 2.
#define ADC_CDR3 (*((reg32_t *)(ADC_BASE + ADC_CDR3_OFF))) ///< Channel data register 3.
#define ADC_CDR4 (*((reg32_t *)(ADC_BASE + ADC_CDR4_OFF))) ///< Channel data register 4.
#define ADC_CDR5 (*((reg32_t *)(ADC_BASE + ADC_CDR5_OFF))) ///< Channel data register 5.
#define ADC_CDR6 (*((reg32_t *)(ADC_BASE + ADC_CDR6_OFF))) ///< Channel data register 6.
#define ADC_CDR7 (*((reg32_t *)(ADC_BASE + ADC_CDR7_OFF))) ///< Channel data register 7.
/* \} */
#endif /* AT91_ADC_H */

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/**
* \file
* <!--
* This file is part of BeRTOS.
*
* Bertos is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* As a special exception, you may use this file as part of a free software
* library without restriction. Specifically, if other files instantiate
* templates or use macros or inline functions from this file, or you compile
* this file and link it with other files to produce an executable, this
* file does not by itself cause the resulting executable to be covered by
* the GNU General Public License. This exception does not however
* invalidate any other reasons why the executable file might be covered by
* the GNU General Public License.
*
* Copyright 2007 Develer S.r.l. (http://www.develer.com/)
*
* -->
*
*
* \author Francesco Sacchi <batt@develer.com>
*
* AT91 advanced interrupt controller.
* This file is based on NUT/OS implementation. See license below.
*/
/*
* Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
* SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* For additional information see http://www.ethernut.de/
*/
#ifndef AT91_AIC_H
#define AT91_AIC_H
#include <cfg/compiler.h>
/**
* Source mode register array.
*/
#define AIC_SMR(i) (*((reg32_t *)(AIC_BASE + (i) * 4)))
/**
* Priority mask.
* Priority levels can be between 0 (lowest) and 7 (highest).
*/
#define AIC_PRIOR_MASK 0x00000007
/**
* Interrupt source type mask.
* Internal interrupts can level sensitive or edge triggered.
*
* External interrupts can triggered on positive or negative levels or
* on rising or falling edges.
*/
/*\{*/
#define AIC_SRCTYPE_MASK 0x00000060
#define AIC_SRCTYPE_INT_LEVEL_SENSITIVE 0x00000000 ///< Internal level sensitive.
#define AIC_SRCTYPE_INT_EDGE_TRIGGERED 0x00000020 ///< Internal edge triggered.
#define AIC_SRCTYPE_EXT_LOW_LEVEL 0x00000000 ///< External low level.
#define AIC_SRCTYPE_EXT_NEGATIVE_EDGE 0x00000020 ///< External falling edge.
#define AIC_SRCTYPE_EXT_HIGH_LEVEL 0x00000040 ///< External high level.
#define AIC_SRCTYPE_EXT_POSITIVE_EDGE 0x00000060 ///< External rising edge.
/*\}*/
/**
* Type for interrupt handlers.
*/
typedef void (*irq_handler_t)(void);
/** Interrupt Source Vector Registers */
/*\{*/
/** Source vector register array.
*
* Stores the addresses of the corresponding interrupt handlers.
*/
#define AIC_SVR(i) (*((volatile irq_handler_t *)(AIC_BASE + 0x80 + (i) * 4)))
/*\}*/
/** Interrupt Vector Register */
/*\{*/
#define AIC_IVR_OFF 0x00000100 ///< IRQ vector register offset.
#define AIC_IVR (*((reg32_t *)(AIC_BASE + AIC_IVR_OFF))) ///< IRQ vector register address.
/*\}*/
/** Fast Interrupt Vector Register */
/*\{*/
#define AIC_FVR_OFF 0x00000104 ///< FIQ vector register offset.
#define AIC_FVR (*((reg32_t *)(AIC_BASE + AIC_FVR_OFF))) ///< FIQ vector register address.
/*\}*/
/** Interrupt Status Register */
/*\{*/
#define AIC_ISR_OFF 0x00000108 ///< Interrupt status register offset.
#define AIC_ISR (*((reg32_t *)(AIC_BASE + AIC_ISR_OFF))) ///< Interrupt status register address.
#define AIC_IRQID_MASK 0x0000001F ///< Current interrupt identifier mask.
/*\}*/
/** Interrupt Pending Register */
/*\{*/
#define AIC_IPR_OFF 0x0000010C ///< Interrupt pending register offset.
#define AIC_IPR (*((reg32_t *)(AIC_BASE + AIC_IPR_OFF))) ///< Interrupt pending register address.
/*\}*/
/** Interrupt Mask Register */
/*\{*/
#define AIC_IMR_OFF 0x00000110 ///< Interrupt mask register offset.
#define AIC_IMR (*((reg32_t *)(AIC_BASE + AIC_IMR_OFF))) ///< Interrupt mask register address.
/*\}*/
/** Interrupt Core Status Register */
/*\{*/
#define AIC_CISR_OFF 0x00000114 ///< Core interrupt status register offset.
#define AIC_CISR (*((reg32_t *)(AIC_BASE + AIC_CISR_OFF))) ///< Core interrupt status register address.
#define AIC_NFIQ 1 ///< Core FIQ Status
#define AIC_NIRQ 2 ///< Core IRQ Status
/*\}*/
/** Interrupt Enable Command Register */
/*\{*/
#define AIC_IECR_OFF 0x00000120 ///< Interrupt enable command register offset.
#define AIC_IECR (*((reg32_t *)(AIC_BASE + AIC_IECR_OFF))) ///< Interrupt enable command register address.
/*\}*/
/** Interrupt Disable Command Register */
/*\{*/
#define AIC_IDCR_OFF 0x00000124 ///< Interrupt disable command register offset.
#define AIC_IDCR (*((reg32_t *)(AIC_BASE + AIC_IDCR_OFF))) ///< Interrupt disable command register address.
/*\}*/
/** Interrupt Clear Command Register */
/*\{*/
#define AIC_ICCR_OFF 0x00000128 ///< Interrupt clear command register offset.
#define AIC_ICCR (*((reg32_t *)(AIC_BASE + AIC_ICCR_OFF))) ///< Interrupt clear command register address.
/*\}*/
/** Interrupt Set Command Register */
/*\{*/
#define AIC_ISCR_OFF 0x0000012C ///< Interrupt set command register offset.
#define AIC_ISCR (*((reg32_t *)(AIC_BASE + AIC_ISCR_OFF))) ///< Interrupt set command register address.
/*\}*/
/** End Of Interrupt Command Register */
/*\{*/
#define AIC_EOICR_OFF 0x00000130 ///< End of interrupt command register offset.
#define AIC_EOICR (*((reg32_t *)(AIC_BASE + AIC_EOICR_OFF))) ///< End of interrupt command register address.
/*\}*/
/** Spurious Interrupt Vector Register */
/*\{*/
#define AIC_SPU_OFF 0x00000134 ///< Spurious vector register offset.
#define AIC_SPU (*((reg32_t *)(AIC_BASE + AIC_SPU_OFF)== ///< Spurious vector register address.
/*\}*/
/** Debug Control Register */
/*\{*/
#define AIC_DCR_OFF 0x0000138 ///< Debug control register offset.
#define AIC_DCR (*((reg32_t *)(AIC_BASE + AIC_DCR_OFF))) ///< Debug control register address.
/*\}*/
/** Fast Forcing Enable Register */
/*\{*/
#define AIC_FFER_OFF 0x00000140 ///< Fast forcing enable register offset.
#define AIC_FFER (*((reg32_t *)(AIC_BASE + AIC_FFER_OFF))) ///< Fast forcing enable register address.
/*\}*/
/** Fast Forcing Disable Register */
/*\{*/
#define AIC_FFDR_OFF 0x00000144 ///< Fast forcing disable register address.
#define AIC_FFDR (*((reg32_t *)(AIC_BASE + AIC_FFDR_OFF))) ///< Fast forcing disable register address.
/*\}*/
/** Fast Forcing Status Register */
/*\{*/
#define AIC_FFSR_OFF 0x00000148 ///< Fast forcing status register address.
#define AIC_FFSR (*((reg32_t *)(AIC_BASE + AIC_FFSR_OFF))) ///< Fast forcing status register address.
/*\}*/
#endif /* AT91_AIC_H */

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/**
* \file
* <!--
* This file is part of BeRTOS.
*
* Bertos is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* As a special exception, you may use this file as part of a free software
* library without restriction. Specifically, if other files instantiate
* templates or use macros or inline functions from this file, or you compile
* this file and link it with other files to produce an executable, this
* file does not by itself cause the resulting executable to be covered by
* the GNU General Public License. This exception does not however
* invalidate any other reasons why the executable file might be covered by
* the GNU General Public License.
*
* Copyright 2007 Develer S.r.l. (http://www.develer.com/)
*
* -->
*
*
* \author Francesco Sacchi <batt@develer.com>
*
* AT91 Debug unit.
* This file is based on NUT/OS implementation. See license below.
*/
/*
* Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
* SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* For additional information see http://www.ethernut.de/
*/
#ifndef AT91_DBGU_H
#define AT91_DBGU_H
#define DBGU_CR (*((reg32_t *)(DBGU_BASE + US_CR_OFF))) ///<DBGU control register address.
#define DBGU_MR (*((reg32_t *)(DBGU_BASE + US_MR_OFF))) ///<DBGU mode register address.
#define DBGU_IER (*((reg32_t *)(DBGU_BASE + US_IER_OFF))) ///<DBGU interrupt enable register address.
#define DBGU_IDR (*((reg32_t *)(DBGU_BASE + US_IDR_OFF))) ///<DBGU interrupt disable register address.
#define DBGU_IMR (*((reg32_t *)(DBGU_BASE + US_IMR_OFF))) ///<DBGU interrupt mask register address.
#define DBGU_SR (*((reg32_t *)(DBGU_BASE + US_CSR_OFF))) ///<DBGU status register address.
#define DBGU_RHR (*((reg32_t *)(DBGU_BASE + US_RHR_OFF))) ///<DBGU receiver holding register address.
#define DBGU_THR (*((reg32_t *)(DBGU_BASE + US_THR_OFF))) ///<DBGU transmitter holding register address.
#define DBGU_BRGR (*((reg32_t *)(DBGU_BASE + US_BRGR_OFF))) ///<DBGU baud rate register address.
#define DBGU_CIDR_OFF 0x00000040 ///<DBGU chip ID register offset.
#define DBGU_CIDR (*((reg32_t *)(DBGU_BASE + DBGU_CIDR_OFF))) ///<DBGU chip ID register.
#define DBGU_EXID_OFF 0x00000044 ///<DBGU chip ID extension register offset.
#define DBGU_EXID (*((reg32_t *)(DBGU_BASE + DBGU_EXID_OFF))) ///<DBGU chip ID extension register.
#define DBGU_FNR_OFF 0x00000048 ///<DBGU force NTRST register offset.
#define DBGU_FNR (*((reg32_t *)(DBGU_BASE + DBGU_FNR_OFF))) ///<DBGU force NTRST register.
#if defined(DBGU_HAS_PDC)
#define DBGU_RPR (*((reg32_t *)(DBGU_BASE + PERIPH_RPR_OFF))) ///<PDC receive pointer register.
#define DBGU_RCR (*((reg32_t *)(DBGU_BASE + PERIPH_RCR_OFF))) ///<PDC receive counter register.
#define DBGU_TPR (*((reg32_t *)(DBGU_BASE + PERIPH_TPR_OFF))) ///<PDC transmit pointer register.
#define DBGU_TCR (*((reg32_t *)(DBGU_BASE + PERIPH_TCR_OFF))) ///<PDC transmit counter register.
#define DBGU_RNPR (*((reg32_t *)(DBGU_BASE + PERIPH_RNPR_OFF))) ///<PDC receive next pointer register.
#define DBGU_RNCR (*((reg32_t *)(DBGU_BASE + PERIPH_RNCR_OFF))) ///<PDC receive next counter register.
#define DBGU_TNPR (*((reg32_t *)(DBGU_BASE + PERIPH_TNPR_OFF))) ///<PDC transmit next pointer register.
#define DBGU_TNCR (*((reg32_t *)(DBGU_BASE + PERIPH_TNCR_OFF))) ///<PDC transmit next counter register.
#define DBGU_PTCR (*((reg32_t *)(DBGU_BASE + PERIPH_PTCR_OFF))) ///<PDC transfer control register.
#define DBGU_PTSR (*((reg32_t *)(DBGU_BASE + PERIPH_PTSR_OFF))) ///<PDC transfer status register.
#endif
#endif /* AT91_DBGU_H */

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/**
* \file
* <!--
* This file is part of BeRTOS.
*
* Bertos is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* As a special exception, you may use this file as part of a free software
* library without restriction. Specifically, if other files instantiate
* templates or use macros or inline functions from this file, or you compile
* this file and link it with other files to produce an executable, this
* file does not by itself cause the resulting executable to be covered by
* the GNU General Public License. This exception does not however
* invalidate any other reasons why the executable file might be covered by
* the GNU General Public License.
*
* Copyright 2009 Develer S.r.l. (http://www.develer.com/)
*
* -->
*
* \author Daniele Basile <asterix@develer.com>
*
* AT91 Ethernet MAC 10/100 controller.
* This file is based on NUT/OS implementation. See license below.
*/
/*
* Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
* SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* For additional information see http://www.ethernut.de/
*/
#ifndef AT91_EMAC_H
#define AT91_EMAC_H
/**
*
* Network Control Register
*
*/
/* \{ */
#define EMAC_NCR_OFF 0x00000000 ///< Network control register offset.
#define EMAC_NCR (*((reg32_t *)(EMAC_BASE + EMAC_NCR_OFF))) ///< Network Control register address.
#define EMAC_LB 0 ///< PHY loopback.
#define EMAC_LLB 1 ///< EMAC loopback.
#define EMAC_RE 2 ///< Receive enable.
#define EMAC_TE 3 ///< Transmit enable.
#define EMAC_MPE 4 ///< Management port enable.
#define EMAC_CLRSTAT 5 ///< Clear statistics registers.
#define EMAC_INCSTAT 6 ///< Increment statistics registers.
#define EMAC_WESTAT 7 ///< Write enable for statistics registers.
#define EMAC_BP 8 ///< Back pressure.
#define EMAC_TSTART 9 ///< Start Transmission.
#define EMAC_THALT 10 ///< Transmission halt.
// Not in sam7x
//#define EMAC_TPFR 11 ///< Transmit pause frame.
//#define EMAC_TZQ 12 ///< Transmit zero quantum pause frame.
/* \} */
/**
* Network Configuration Register
*
*/
/* \{ */
#define EMAC_NCFGR_OFF 0x00000004 ///< Network configuration register offset.
#define EMAC_NCFGR (*((reg32_t *)(EMAC_BASE + EMAC_NCFGR_OFF))) ///< Network configuration register address.
#define EMAC_SPD 0 ///< Speed, set for 100Mb.
#define EMAC_FD 1 ///< Full duplex.
#define EMAC_JFRAME 3 ///< Jumbo Frames.
#define EMAC_CAF 4 ///< Copy all frames.
#define EMAC_NBC 5 ///< No broadcast.
#define EMAC_MTI 6 ///< Multicast hash event enable.
#define EMAC_UNI 7 ///< Unicast hash enable.
#define EMAC_BIG 8 ///< Receive 1522 bytes.
// Not in sam7x
//#define EMAC_EAE 9 ///< External address match enable.
#define EMAC_CLK 0x00000C00 ///< Clock divider mask.
#define EMAC_CLK_HCLK_8 0x00000000 ///< HCLK divided by 8.
#define EMAC_CLK_HCLK_16 0x00000400 ///< HCLK divided by 16.
#define EMAC_CLK_HCLK_32 0x00000800 ///< HCLK divided by 32.
#define EMAC_CLK_HCLK_64 0x00000C00 ///< HCLK divided by 64.
#define EMAC_RTY 12 ///< Retry test.
#define EMAC_PAE 13 ///< Pause enable.
#define EMAC_RBOF 0x0000C000 ///< Receive buffer offset.
#define EMAC_RBOF_OFFSET_0 0x00000000 ///< No offset from start of receive buffer.
#define EMAC_RBOF_OFFSET_1 0x00004000 ///< One byte offset from start of receive buffer.
#define EMAC_RBOF_OFFSET_2 0x00008000 ///< Two bytes offset from start of receive buffer.
#define EMAC_RBOF_OFFSET_3 0x0000C000 ///< Three bytes offset from start of receive buffer.
#define EMAC_RLCE 16 ///< Receive length field checking enable.
#define EMAC_DRFCS 17 ///< Discard receive FCS.
#define EMAC_EFRHD 18 ///< Allow receive during transmit in half duplex.
#define EMAC_IRXFCS 19 ///< Ignore received FCS.
/* \} */
/**
* Network Status Register
*
*/
/* \{ */
#define EMAC_NSR_OFF 0x00000008 ///< Network Status register offset.
#define EMAC_NSR (*((reg32_t *)(EMAC_BASE + EMAC_NSR_OFF))) ///< Network Status register address.
// Not in sam7x
//#define EMAC_LINKR 0 ///< .
#define EMAC_MDIO 1 ///< Status of MDIO input pin.
#define EMAC_IDLE 2 ///< Set when PHY is running.
/* \} */
/**
* Transmit Status Register
*/
/* \{ */
#define EMAC_TSR_OFF 0x00000014 ///< Transmit Status register offset.
#define EMAC_TSR (*((reg32_t *)(EMAC_BASE + EMAC_TSR_OFF))) ///< Transmit Status register address.
#define EMAC_UBR 0 ///< Used bit read.
#define EMAC_COL 1 ///< Collision occurred.
#define EMAC_RLES 2 ///< Retry limit exceeded.
#define EMAC_TGO 3 ///< Transmit active.
#define EMAC_BEX 4 ///< Buffers exhausted mid frame.
#define EMAC_COMP 5 ///< Transmit complete.
#define EMAC_UND 6 ///< Transmit underrun.
/* \} */
/**
* Buffer Queue Pointer Register
*
*/
/* \{ */
#define EMAC_RBQP_OFF 0x00000018 ///< Receive buffer queue pointer.
#define EMAC_RBQP (*((reg32_t *)(EMAC_BASE + EMAC_RBQP_OFF))) ///< Receive buffer queue pointer.
#define EMAC_TBQP_OFF 0x0000001C ///< Transmit buffer queue pointer.
#define EMAC_TBQP (*((reg32_t *)(EMAC_BASE + EMAC_TBQP_OFF))) ///< Transmit buffer queue pointer.
/* \} */
/**
* Receive Status Register
*/
/* \{ */
#define EMAC_RSR_OFF 0x00000020 ///< Receive status register offset.
#define EMAC_RSR (*((reg32_t *)(EMAC_BASE + EMAC_RSR_OFF))) ///< Receive status register address.
#define EMAC_BNA 0 ///< Buffer not available.
#define EMAC_REC 1 ///< Frame received.
#define EMAC_OVR 2 ///< Receive overrun.
/* \} */
/** Interrupt Registers */
/* \{ */
#define EMAC_ISR_OFF 0x00000024 ///< Status register offset.
#define EMAC_ISR (*((reg32_t *)(EMAC_BASE + EMAC_ISR_OFF))) ///< Status register address.
#define EMAC_IER_OFF 0x00000028 ///< Enable register offset.
#define EMAC_IER (*((reg32_t *)(EMAC_BASE + EMAC_IER_OFF))) ///< Enable register address.
#define EMAC_IDR_OFF 0x0000002C ///< Disable register offset.
#define EMAC_IDR (*((reg32_t *)(EMAC_BASE + EMAC_IDR_OFF))) ///< Disable register address.
#define EMAC_IMR_OFF 0x00000030 ///< Mask register offset.
#define EMAC_IMR (*((reg32_t *)(EMAC_BASE + EMAC_IMR_OFF))) ///< Mask register address.
#define EMAC_MFD 0 ///< Management frame done.
#define EMAC_RCOMP 1 ///< Receive complete.
#define EMAC_RXUBR 2 ///< Receive used bit read.
#define EMAC_TXUBR 3 ///< Transmit used bit read.
#define EMAC_TUND 4 ///< Ethernet transmit buffer underrun.
#define EMAC_RLEX 5 ///< Retry limit exceeded.
#define EMAC_TXERR 6 ///< Transmit error.
#define EMAC_TCOMP 7 ///< Transmit complete.
//Not in sam7x
//#define EMAC_LINK 8 ///< .
#define EMAC_ROVR 10 ///< Receive overrun.
#define EMAC_HRESP 11 ///< DMA bus error.
#define EMAC_PFR 12 ///< Pause frame received.
#define EMAC_PTZ 13 ///< Pause time zero.
/* \} */
/**
* PHY Maintenance Register
*
*/
/* \{ */
#define EMAC_MAN_OFF 0x00000034 ///< PHY maintenance register offset.
#define EMAC_MAN (*((reg32_t *)(EMAC_BASE + EMAC_MAN_OFF))) ///< PHY maintenance register address.
#define EMAC_DATA 0x0000FFFF ///< PHY data mask.
#define EMAC_CODE 0x00020000 ///< Fixed value.
#define EMAC_REGA 0x007C0000 ///< PHY register address mask.
#define EMAC_REGA_SHIFT 18 ///< PHY register address mask.
#define EMAC_PHYA 0x0F800000 ///< PHY address mask.
#define EMAC_PHYA_SHIFT 23 ///< PHY address mask.
#define EMAC_RW 0x30000000 ///< PHY read/write command mask.
#define EMAC_RW_READ 0x20000000 ///< PHY read command.
#define EMAC_RW_WRITE 0x10000000 ///< PHY write command.
#define EMAC_SOF 0x40000000 ///< Fixed value.
/* \} */
/**
* Pause Time Register
*
*/
/* \{ */
#define EMAC_PTR_OFF 0x00000038 ///< Pause time register offset.
#define EMAC_PTR (*((reg32_t *)(EMAC_BASE + EMAC_PTR_OFF))) ///< Pause time register address.
#define EMAC_PTIME 0x0000FFFF ///< Pause time mask.
/* \} */
/**
* Statistics Registers
*/
/* \{ */
#define EMAC_PFRR_OFF 0x0000003C ///< Pause frames received register offset.
#define EMAC_PFRR (*((reg32_t *)(EMAC_BASE + EMAC_PFRR_OFF))) ///< Pause frames received register address.
#define EMAC_FTO_OFF 0x00000040 ///< Frames transmitted OK register offset.
#define EMAC_FTO (*((reg32_t *)(EMAC_BASE + EMAC_FTO_OFF))) ///< Frames transmitted OK register address.
#define EMAC_SCF_OFF 0x00000044 ///< Single collision frame register offset.
#define EMAC_SCF (*((reg32_t *)(EMAC_BASE + EMAC_SCF_OFF))) ///< Single collision frame register address.
#define EMAC_MCF_OFF 0x00000048 ///< Multiple collision frame register offset.
#define EMAC_MCF (*((reg32_t *)(EMAC_BASE + EMAC_MCF_OFF))) ///< Multiple collision frame register address.
#define EMAC_FRO_OFF 0x0000004C ///< Frames received OK register offset.
#define EMAC_FRO (*((reg32_t *)(EMAC_BASE + EMAC_FRO_OFF))) ///< Frames received OK register address.
#define EMAC_FCSE_OFF 0x00000050 ///< Frame check sequence error register offset.
#define EMAC_FCSE (*((reg32_t *)(EMAC_BASE + EMAC_FCSE_OFF))) ///< Frame check sequence error register address.
#define EMAC_ALE_OFF 0x00000054 ///< Alignment error register offset.
#define EMAC_ALE (*((reg32_t *)(EMAC_BASE + EMAC_ALE_OFF))) ///< Alignment error register address.
#define EMAC_DTF_OFF 0x00000058 ///< Deferred transmission frame register offset.
#define EMAC_DTF (*((reg32_t *)(EMAC_BASE + EMAC_DTF_OFF))) ///< Deferred transmission frame register address.
#define EMAC_LCOL_OFF 0x0000005C ///< Late collision register offset.
#define EMAC_LCOL (*((reg32_t *)(EMAC_BASE + EMAC_LCOL_OFF))) ///< Late collision register address.
#define EMAC_ECOL_OFF 0x00000060 ///< Excessive collision register offset.
#define EMAC_ECOL (*((reg32_t *)(EMAC_BASE + EMAC_ECOL_OFF))) ///< Excessive collision register address.
#define EMAC_TUNDR_OFF 0x00000064 ///< Transmit underrun error register offset.
#define EMAC_TUNDR (*((reg32_t *)(EMAC_BASE + EMAC_TUNDR_OFF))) ///< Transmit underrun error register address.
#define EMAC_CSE_OFF 0x00000068 ///< Carrier sense error register offset.
#define EMAC_CSE (*((reg32_t *)(EMAC_BASE + EMAC_CSE_OFF))) ///< Carrier sense error register address.
#define EMAC_RRE_OFF 0x0000006C ///< Receive resource error register offset.
#define EMAC_RRE (*((reg32_t *)(EMAC_BASE + EMAC_RRE_OFF))) ///< Receive resource error register address.
#define EMAC_ROV_OFF 0x00000070 ///< Receive overrun errors register offset.
#define EMAC_ROV (*((reg32_t *)(EMAC_BASE + EMAC_ROV_OFF))) ///< Receive overrun errors register address.
#define EMAC_RSE_OFF 0x00000074 ///< Receive symbol errors register offset.
#define EMAC_RSE (*((reg32_t *)(EMAC_BASE + EMAC_RSE_OFF))) ///< Receive symbol errors register address.
#define EMAC_ELE_OFF 0x00000078 ///< Excessive length errors register offset.
#define EMAC_ELE (*((reg32_t *)(EMAC_BASE + EMAC_ELE_OFF))) ///< Excessive length errors register address.
#define EMAC_RJA_OFF 0x0000007C ///< Receive jabbers register offset.
#define EMAC_RJA (*((reg32_t *)(EMAC_BASE + EMAC_RJA_OFF))) ///< Receive jabbers register address.
#define EMAC_USF_OFF 0x00000080 ///< Undersize frames register offset.
#define EMAC_USF (*((reg32_t *)(EMAC_BASE + EMAC_USF_OFF))) ///< Undersize frames register address.
#define EMAC_STE_OFF 0x00000084 ///< SQE test error register offset.
#define EMAC_STE (*((reg32_t *)(EMAC_BASE + EMAC_STE_OFF))) ///< SQE test error register address.
#define EMAC_RLE_OFF 0x00000088 ///< Receive length field mismatch register offset.
#define EMAC_RLE (*((reg32_t *)(EMAC_BASE + EMAC_RLE_OFF))) ///< Receive length field mismatch register address.
// Not in sam7x
//#define EMAC_TPF_OFF 0x0000008C ///< Transmitted pause frames register offset.
//#define EMAC_TPF (*((reg32_t *)(EMAC_BASE + EMAC_TPF_OFF) ///< Transmitted pause frames register address.
/* \} */
/**
* MAC Adressing Registers
*
*/
/* \{ */
#define EMAC_HRB_OFF 0x00000090 ///< Hash address bottom[31:0].
#define EMAC_HRB (*((reg32_t *)(EMAC_BASE + EMAC_HRB_OFF))) ///< Hash address bottom[31:0].
#define EMAC_HRT_OFF 0x00000094 ///< Hash address top[63:32].
#define EMAC_HRT (*((reg32_t *)(EMAC_BASE + EMAC_HRT_OFF))) ///< Hash address top[63:32].
#define EMAC_SA1L_OFF 0x00000098 ///< Specific address 1 bottom, first 4 bytes.
#define EMAC_SA1L (*((reg32_t *)(EMAC_BASE + EMAC_SA1L_OFF))) ///< Specific address 1 bottom, first 4 bytes.
#define EMAC_SA1H_OFF 0x0000009C ///< Specific address 1 top, last 2 bytes.
#define EMAC_SA1H (*((reg32_t *)(EMAC_BASE + EMAC_SA1H_OFF))) ///< Specific address 1 top, last 2 bytes.
#define EMAC_SA2L_OFF 0x000000A0 ///< Specific address 2 bottom, first 4 bytes.
#define EMAC_SA2L (*((reg32_t *)(EMAC_BASE + EMAC_SA2L_OFF))) ///< Specific address 2 bottom, first 4 bytes.
#define EMAC_SA2H_OFF 0x000000A4 ///< Specific address 2 top, last 2 bytes.
#define EMAC_SA2H (*((reg32_t *)(EMAC_BASE + EMAC_SA2H_OFF))) ///< Specific address 2 top, last 2 bytes.
#define EMAC_SA3L_OFF 0x000000A8 ///< Specific address 3 bottom, first 4 bytes.
#define EMAC_SA3L (*((reg32_t *)(EMAC_BASE + EMAC_SA3L_OFF))) ///< Specific address 3 bottom, first 4 bytes.
#define EMAC_SA3H_OFF 0x000000AC ///< Specific address 3 top, last 2 bytes.
#define EMAC_SA3H (*((reg32_t *)(EMAC_BASE + EMAC_SA3H_OFF))) ///< Specific address 3 top, last 2 bytes.
#define EMAC_SA4L_OFF 0x000000B0 ///< Specific address 4 bottom, first 4 bytes.
#define EMAC_SA4L (*((reg32_t *)(EMAC_BASE + EMAC_SA4L_OFF))) ///< Specific address 4 bottom, first 4 bytes.
#define EMAC_SA4H_OFF 0x000000B4 ///< Specific address 4 top, last 2 bytes.
#define EMAC_SA4H (*((reg32_t *)(EMAC_BASE + EMAC_SA4H_OFF))) ///< Specific address 4 top, last 2 bytes.
/* \} */
/**
* Type ID Register
*
*/
/* \{ */
#define EMAC_TID_OFF 0x000000B8 ///< Type ID checking register offset.
#define EMAC_TID (*((reg32_t *)(EMAC_BASE + EMAC_TID_OFF))) ///< Type ID checking register address.
// Not in sam7x
//#define EMAC_TPQ_OFF 0x000000BC ///< Transmit pause quantum register offset.
//#define EMAC_TPQ (*((reg32_t *)(EMAC_BASE + EMAC_TPQ_OFF))) ///< Transmit pause quantum register address.
/* \} */
/**
* User Input/Output Register
*
*/
/* \{ */
#define EMAC_USRIO_OFF 0x000000C0 ///< User input/output register offset.
#define EMAC_USRIO (*((reg32_t *)(EMAC_BASE + EMAC_USRIO_OFF))) ///< User input/output register address.
#define EMAC_RMII 0 ///< Enable reduced MII.
#define EMAC_CLKEN 1 ///< Enable tranceiver input clock.
/* \} */
// Not in sam7x
/*
* Wake On LAN Register
*
*
* \{ *
#define EMAC_WOL_OFF 0x000000C4 ///< Wake On LAN register offset.
#define EMAC_WOL (*((reg32_t *)(EMAC_BASE + EMAC_WOL_OFF) ///< Wake On LAN register address.
#define EMAC_IP 0x0000FFFF ///< ARP request IP address mask.
#define EMAC_MAG 0x00010000 ///< Magic packet event enable.
#define EMAC_ARP 0x00020000 ///< ARP request event enable.
#define EMAC_SA1 0x00040000 ///< Specific address register 1 event enable.
* \} *
** Revision Register *
* \{ *
#define EMAC_REV_OFF 0x000000FC ///< Revision register offset.
#define EMAC_REV (*((reg32_t *)(EMAC_BASE + EMAC_REV_OFF) ///< Revision register address.
#define EMAC_REVREF 0x0000FFFF ///< Revision.
#define EMAC_PARTREF 0xFFFF0000 ///< Part.
* \} *
*/
#endif /* AT91_EMAC_H */

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/**
* \file
* <!--
* This file is part of BeRTOS.
*
* Bertos is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* As a special exception, you may use this file as part of a free software
* library without restriction. Specifically, if other files instantiate
* templates or use macros or inline functions from this file, or you compile
* this file and link it with other files to produce an executable, this
* file does not by itself cause the resulting executable to be covered by
* the GNU General Public License. This exception does not however
* invalidate any other reasons why the executable file might be covered by
* the GNU General Public License.
*
* Copyright 2007 Develer S.r.l. (http://www.develer.com/)
*
* -->
*
*
* \author Francesco Sacchi <batt@develer.com>
*
* AT91 Memory controller.
* This file is based on NUT/OS implementation. See license below.
*/
/*
* Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
* SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* For additional information see http://www.ethernut.de/
*/
#ifndef AT91_MC_H
#define AT91_MC_H
#define MC_RCR_OFF 0x00000000 ///< MC remap control register offset.
#define MC_RCR (*((reg32_t *)(MC_BASE + MC_RCR_OFF))) ///< MC remap control register address.
#define MC_RCB 0 ///< Remap command.
#define MC_ASR_OFF 0x00000004 ///< MC abort status register offset.
#define MC_ASR (*((reg32_t *)(MC_BASE + MC_ASR_OFF))) ///< MC abort status register address.
#define MC_UNDADD 0 ///< Undefined Addess Abort status.
#define MC_MISADD 1 ///< Misaligned Addess Abort status.
#define MC_ABTSZ_MASK 0x00000300 ///< Abort size status mask.
#define MC_ABTSZ_BYTE 0x00000000 ///< Byte size abort.
#define MC_ABTSZ_HWORD 0x00000100 ///< Half-word size abort.
#define MC_ABTSZ_WORD 0x00000200 ///< Word size abort.
#define MC_ABTTYP_MASK 0x00000C00 ///< Abort type status mask.
#define MC_ABTTYP_DATAR 0x00000000 ///< Data read abort.
#define MC_ABTTYP_DATAW 0x00000400 ///< Data write abort.
#define MC_ABTTYP_FETCH 0x00000800 ///< Code fetch abort.
#define MC_MST_PDC 0x00020000 ///< PDC abort source.
#define MC_MST_ARM 0x00040000 ///< ARM abort source.
#define MC_SVMST_PDC 0x02000000 ///< Saved PDC abort source.
#define MC_SVMST_ARM 0x04000000 ///< Saved ARM abort source.
#define MC_AASR_OFF 0x00000008 ///< MC abort address status register offset.
#define MC_AASR (*((reg32_t *)(MC_BASE + MC_AASR_OFF))) ///< MC abort address status register address.
#define MC_FMR_OFF 0x00000060 ///< MC flash mode register offset.
#define MC_FMR (*((reg32_t *)(MC_BASE + MC_FMR_OFF))) ///< MC flash mode register address.
#define MC_FRDY 0 ///< Flash ready.
#define MC_LOCKE 2 ///< Lock error.
#define MC_PROGE 3 ///< Programming error.
#define MC_NEBP 7 ///< No erase before programming.
#define MC_FWS_MASK 0x00000300 ///< Flash wait state mask.
#define MC_FWS_1R2W 0x00000000 ///< 1 cycle for read, 2 for write operations.
#define MC_FWS_2R3W 0x00000100 ///< 2 cycles for read, 3 for write operations.
#define MC_FWS_3R4W 0x00000200 ///< 3 cycles for read, 4 for write operations.
#define MC_FWS_4R4W 0x00000300 ///< 4 cycles for read and write operations.
#define MC_FMCN_MASK 0x00FF0000 ///< Flash microsecond cycle number mask.
#define MC_FMCN_SHIFT 16 ///< Flash microsecond cycle number shift.
#define MC_FCR_OFF 0x00000064 ///< MC flash command register offset.
#define MC_FCR (*((reg32_t *)(MC_BASE + MC_FCR_OFF))) ///< MC flash command register address.
#define MC_FCMD_MASK 0x0000000F ///< Flash command mask.
#define MC_FCMD_NOP 0x00000000 ///< No command.
#define MC_FCMD_WP 0x00000001 ///< Write page.
#define MC_FCMD_SLB 0x00000002 ///< Set lock bit.
#define MC_FCMD_WPL 0x00000003 ///< Write page and lock.
#define MC_FCMD_CLB 0x00000004 ///< Clear lock bit.
#define MC_FCMD_EA 0x00000008 ///< Erase all.
#define MC_FCMD_SGPB 0x0000000B ///< Set general purpose NVM bit.
#define MC_FCMD_CGPB 0x0000000D ///< Clear general purpose NVM bit.
#define MC_FCMD_SSB 0x0000000F ///< Set security bit.
#define MC_PAGEN_MASK 0x0003FF00 ///< Page number mask.
#define MC_KEY 0x5A000000 ///< Writing protect key.
#define MC_FSR_OFF 0x00000068 ///< MC flash status register offset.
#define MC_FSR (*((reg32_t *)(MC_BASE + MC_FSR_OFF))) ///< MC flash status register address.
#define MC_SECURITY 4 ///< Security bit status.
#define MC_GPNVM0 8 ///< General purpose NVM bit 0.
#define MC_GPNVM1 9 ///< General purpose NVM bit 1.
#define MC_GPNVM2 10 ///< General purpose NVM bit 2.
#define MC_LOCKS0 16 ///< Lock region 0 lock status.
#define MC_LOCKS1 17 ///< Lock region 1 lock status.
#define MC_LOCKS2 18 ///< Lock region 2 lock status.
#define MC_LOCKS3 19 ///< Lock region 3 lock status.
#define MC_LOCKS4 20 ///< Lock region 4 lock status.
#define MC_LOCKS5 21 ///< Lock region 5 lock status.
#define MC_LOCKS6 22 ///< Lock region 6 lock status.
#define MC_LOCKS7 23 ///< Lock region 7 lock status.
#define MC_LOCKS8 24 ///< Lock region 8 lock status.
#define MC_LOCKS9 25 ///< Lock region 9 lock status.
#define MC_LOCKS10 26 ///< Lock region 10 lock status.
#define MC_LOCKS11 27 ///< Lock region 11 lock status.
#define MC_LOCKS12 28 ///< Lock region 12 lock status.
#define MC_LOCKS13 29 ///< Lock region 13 lock status.
#define MC_LOCKS14 30 ///< Lock region 14 lock status.
#define MC_LOCKS15 31 ///< Lock region 15 lock status.
#endif /* AT91_MC_H */

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/**
* \file
* <!--
* This file is part of BeRTOS.
*
* Bertos is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* As a special exception, you may use this file as part of a free software
* library without restriction. Specifically, if other files instantiate
* templates or use macros or inline functions from this file, or you compile
* this file and link it with other files to produce an executable, this
* file does not by itself cause the resulting executable to be covered by
* the GNU General Public License. This exception does not however
* invalidate any other reasons why the executable file might be covered by
* the GNU General Public License.
*
* Copyright 2007 Develer S.r.l. (http://www.develer.com/)
*
* -->
*
*
* \author Francesco Sacchi <batt@develer.com>
*
* AT91 Parallel input/output controller.
* This file is based on NUT/OS implementation. See license below.
*/
/*
* Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
* SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* For additional information see http://www.ethernut.de/
*/
#ifndef AT91_PIO_H
#define AT91_PIO_H
/** PIO Register Offsets */
/*\{*/
#define PIO_PER_OFF 0x00000000 ///< PIO enable register offset.
#define PIO_PDR_OFF 0x00000004 ///< PIO disable register offset.
#define PIO_PSR_OFF 0x00000008 ///< PIO status register offset.
#define PIO_OER_OFF 0x00000010 ///< Output enable register offset.
#define PIO_ODR_OFF 0x00000014 ///< Output disable register offset.
#define PIO_OSR_OFF 0x00000018 ///< Output status register offset.
#define PIO_IFER_OFF 0x00000020 ///< Input filter enable register offset.
#define PIO_IFDR_OFF 0x00000024 ///< Input filter disable register offset.
#define PIO_IFSR_OFF 0x00000028 ///< Input filter status register offset.
#define PIO_SODR_OFF 0x00000030 ///< Set output data register offset.
#define PIO_CODR_OFF 0x00000034 ///< Clear output data register offset.
#define PIO_ODSR_OFF 0x00000038 ///< Output data status register offset.
#define PIO_PDSR_OFF 0x0000003C ///< Pin data status register offset.
#define PIO_IER_OFF 0x00000040 ///< Interrupt enable register offset.
#define PIO_IDR_OFF 0x00000044 ///< Interrupt disable register offset.
#define PIO_IMR_OFF 0x00000048 ///< Interrupt mask register offset.
#define PIO_ISR_OFF 0x0000004C ///< Interrupt status register offset.
#if PIO_HAS_MULTIDRIVER
#define PIO_MDER_OFF 0x00000050 ///< Multi-driver enable register offset.
#define PIO_MDDR_OFF 0x00000054 ///< Multi-driver disable register offset.
#define PIO_MDSR_OFF 0x00000058 ///< Multi-driver status register offset.
#endif /* PIO_HAS_MULTIDRIVER */
#if PIO_HAS_PULLUP
#define PIO_PUDR_OFF 0x00000060 ///< Pull-up disable register offset.
#define PIO_PUER_OFF 0x00000064 ///< Pull-up enable register offset.
#define PIO_PUSR_OFF 0x00000068 ///< Pull-up status register offset.
#endif /* PIO_HAS_PULLUP */
#if PIO_HAS_PERIPHERALSELECT
#define PIO_ASR_OFF 0x00000070 ///< PIO peripheral A select register offset.
#define PIO_BSR_OFF 0x00000074 ///< PIO peripheral B select register offset.
#define PIO_ABSR_OFF 0x00000078 ///< PIO peripheral AB status register offset.
#endif /* PIO_HAS_PERIPHERALSELECT */
#if PIO_HAS_OUTPUTWRITEENABLE
#define PIO_OWER_OFF 0x000000A0 ///< PIO output write enable register offset.
#define PIO_OWDR_OFF 0x000000A4 ///< PIO output write disable register offset.
#define PIO_OWSR_OFF 0x000000A8 ///< PIO output write status register offset.
#endif /* PIO_HAS_OUTPUTWRITEENABLE */
/*\}*/
/** Single PIO Register Addresses */
/*\{*/
#if defined(PIO_BASE)
#define PIO_ACCESS(offset) (*((reg32_t *)(PIO_BASE + (offset))))
#define PIO_PER PIO_ACCESS(PIO_PER_OFF) ///< PIO enable register address.
#define PIO_PDR PIO_ACCESS(PIO_PDR_OFF) ///< PIO disable register address.
#define PIO_PSR PIO_ACCESS(PIO_PSR_OFF) ///< PIO status register address.
#define PIO_OER PIO_ACCESS(PIO_OER_OFF) ///< Output enable register address.
#define PIO_ODR PIO_ACCESS(PIO_ODR_OFF) ///< Output disable register address.
#define PIO_OSR PIO_ACCESS(PIO_OSR_OFF) ///< Output status register address.
#define PIO_IFER PIO_ACCESS(PIO_IFER_OFF) ///< Input filter enable register address.
#define PIO_IFDR PIO_ACCESS(PIO_IFDR_OFF) ///< Input filter disable register address.
#define PIO_IFSR PIO_ACCESS(PIO_IFSR_OFF) ///< Input filter status register address.
#define PIO_SODR PIO_ACCESS(PIO_SODR_OFF) ///< Set output data register address.
#define PIO_CODR PIO_ACCESS(PIO_CODR_OFF) ///< Clear output data register address.
#define PIO_ODSR PIO_ACCESS(PIO_ODSR_OFF) ///< Output data status register address.
#define PIO_PDSR PIO_ACCESS(PIO_PDSR_OFF) ///< Pin data status register address.
#define PIO_IER PIO_ACCESS(PIO_IER_OFF) ///< Interrupt enable register address.
#define PIO_IDR PIO_ACCESS(PIO_IDR_OFF) ///< Interrupt disable register address.
#define PIO_IMR PIO_ACCESS(PIO_IMR_OFF) ///< Interrupt mask register address.
#define PIO_ISR PIO_ACCESS(PIO_ISR_OFF) ///< Interrupt status register address.
#if PIO_HAS_MULTIDRIVER
#define PIO_MDER PIO_ACCESS(PIO_MDER_OFF) ///< Multi-driver enable register address.
#define PIO_MDDR PIO_ACCESS(PIO_MDDR_OFF) ///< Multi-driver disable register address.
#define PIO_MDSR PIO_ACCESS(PIO_MDSR_OFF) ///< Multi-driver status register address.
#endif /* PIO_HAS_MULTIDRIVER */
#if PIO_HAS_PULLUP
#define PIO_PUDR PIO_ACCESS(PIO_PUDR_OFF) ///< Pull-up disable register address.
#define PIO_PUER PIO_ACCESS(PIO_PUER_OFF) ///< Pull-up enable register address.
#define PIO_PUSR PIO_ACCESS(PIO_PUSR_OFF) ///< Pull-up status register address.
#endif /* PIO_HAS_PULLUP */
#if PIO_HAS_PERIPHERALSELECT
#define PIO_ASR PIO_ACCESS(PIO_ASR_OFF) ///< PIO peripheral A select register address.
#define PIO_BSR PIO_ACCESS(PIO_BSR_OFF) ///< PIO peripheral B select register address.
#define PIO_ABSR PIO_ACCESS(PIO_ABSR_OFF) ///< PIO peripheral AB status register address.
#endif /* PIO_HAS_PERIPHERALSELECT */
#if PIO_HAS_OUTPUTWRITEENABLE
#define PIO_OWER PIO_ACCESS(PIO_OWER_OFF) ///< PIO output write enable register address.
#define PIO_OWDR PIO_ACCESS(PIO_OWDR_OFF) ///< PIO output write disable register address.
#define PIO_OWSR PIO_ACCESS(PIO_OWSR_OFF) ///< PIO output write status register address.
#endif /* PIO_HAS_OUTPUTWRITEENABLE */
#endif /* PIO_BASE */
/*\}*/
/** PIO A Register Addresses */
/*\{*/
#if defined(PIOA_BASE)
#define PIOA_ACCESS(offset) (*((reg32_t *)(PIOA_BASE + (offset))))
#define PIOA_PER PIOA_ACCESS(PIO_PER_OFF) ///< PIO enable register address.
#define PIOA_PDR PIOA_ACCESS(PIO_PDR_OFF) ///< PIO disable register address.
#define PIOA_PSR PIOA_ACCESS(PIO_PSR_OFF) ///< PIO status register address.
#define PIOA_OER PIOA_ACCESS(PIO_OER_OFF) ///< Output enable register address.
#define PIOA_ODR PIOA_ACCESS(PIO_ODR_OFF) ///< Output disable register address.
#define PIOA_OSR PIOA_ACCESS(PIO_OSR_OFF) ///< Output status register address.
#define PIOA_IFER PIOA_ACCESS(PIO_IFER_OFF) ///< Input filter enable register address.
#define PIOA_IFDR PIOA_ACCESS(PIO_IFDR_OFF) ///< Input filter disable register address.
#define PIOA_IFSR PIOA_ACCESS(PIO_IFSR_OFF) ///< Input filter status register address.
#define PIOA_SODR PIOA_ACCESS(PIO_SODR_OFF) ///< Set output data register address.
#define PIOA_CODR PIOA_ACCESS(PIO_CODR_OFF) ///< Clear output data register address.
#define PIOA_ODSR PIOA_ACCESS(PIO_ODSR_OFF) ///< Output data status register address.
#define PIOA_PDSR PIOA_ACCESS(PIO_PDSR_OFF) ///< Pin data status register address.
#define PIOA_IER PIOA_ACCESS(PIO_IER_OFF) ///< Interrupt enable register address.
#define PIOA_IDR PIOA_ACCESS(PIO_IDR_OFF) ///< Interrupt disable register address.
#define PIOA_IMR PIOA_ACCESS(PIO_IMR_OFF) ///< Interrupt mask register address.
#define PIOA_ISR PIOA_ACCESS(PIO_ISR_OFF) ///< Interrupt status register address.
#if PIO_HAS_MULTIDRIVER
#define PIOA_MDER PIOA_ACCESS(PIO_MDER_OFF) ///< Multi-driver enable register address.
#define PIOA_MDDR PIOA_ACCESS(PIO_MDDR_OFF) ///< Multi-driver disable register address.
#define PIOA_MDSR PIOA_ACCESS(PIO_MDSR_OFF) ///< Multi-driver status register address.
#endif /* PIO_HAS_MULTIDRIVER */
#if PIO_HAS_PULLUP
#define PIOA_PUDR PIOA_ACCESS(PIO_PUDR_OFF) ///< Pull-up disable register address.
#define PIOA_PUER PIOA_ACCESS(PIO_PUER_OFF) ///< Pull-up enable register address.
#define PIOA_PUSR PIOA_ACCESS(PIO_PUSR_OFF) ///< Pull-up status register address.
#endif /* PIO_HAS_PULLUP */
#if PIO_HAS_PERIPHERALSELECT
#define PIOA_ASR PIOA_ACCESS(PIO_ASR_OFF) ///< PIO peripheral A select register address.
#define PIOA_BSR PIOA_ACCESS(PIO_BSR_OFF) ///< PIO peripheral B select register address.
#define PIOA_ABSR PIOA_ACCESS(PIO_ABSR_OFF) ///< PIO peripheral AB status register address.
#endif /* PIO_HAS_PERIPHERALSELECT */
#if PIO_HAS_OUTPUTWRITEENABLE
#define PIOA_OWER PIOA_ACCESS(PIO_OWER_OFF) ///< PIO output write enable register address.
#define PIOA_OWDR PIOA_ACCESS(PIO_OWDR_OFF) ///< PIO output write disable register address.
#define PIOA_OWSR PIOA_ACCESS(PIO_OWSR_OFF) ///< PIO output write status register address.
#endif /* PIO_HAS_OUTPUTWRITEENABLE */
#endif /* PIOA_BASE */
/*\}*/
/** PIO B Register Addresses */
/*\{*/
#if defined(PIOB_BASE)
#define PIOB_ACCESS(offset) (*((reg32_t *)(PIOB_BASE + (offset))))
#define PIOB_PER PIOB_ACCESS(PIO_PER_OFF) ///< PIO enable register address.
#define PIOB_PDR PIOB_ACCESS(PIO_PDR_OFF) ///< PIO disable register address.
#define PIOB_PSR PIOB_ACCESS(PIO_PSR_OFF) ///< PIO status register address.
#define PIOB_OER PIOB_ACCESS(PIO_OER_OFF) ///< Output enable register address.
#define PIOB_ODR PIOB_ACCESS(PIO_ODR_OFF) ///< Output disable register address.
#define PIOB_OSR PIOB_ACCESS(PIO_OSR_OFF) ///< Output status register address.
#define PIOB_IFER PIOB_ACCESS(PIO_IFER_OFF) ///< Input filter enable register address.
#define PIOB_IFDR PIOB_ACCESS(PIO_IFDR_OFF) ///< Input filter disable register address.
#define PIOB_IFSR PIOB_ACCESS(PIO_IFSR_OFF) ///< Input filter status register address.
#define PIOB_SODR PIOB_ACCESS(PIO_SODR_OFF) ///< Set output data register address.
#define PIOB_CODR PIOB_ACCESS(PIO_CODR_OFF) ///< Clear output data register address.
#define PIOB_ODSR PIOB_ACCESS(PIO_ODSR_OFF) ///< Output data status register address.
#define PIOB_PDSR PIOB_ACCESS(PIO_PDSR_OFF) ///< Pin data status register address.
#define PIOB_IER PIOB_ACCESS(PIO_IER_OFF) ///< Interrupt enable register address.
#define PIOB_IDR PIOB_ACCESS(PIO_IDR_OFF) ///< Interrupt disable register address.
#define PIOB_IMR PIOB_ACCESS(PIO_IMR_OFF) ///< Interrupt mask register address.
#define PIOB_ISR PIOB_ACCESS(PIO_ISR_OFF) ///< Interrupt status register address.
#if PIO_HAS_MULTIDRIVER
#define PIOB_MDER PIOB_ACCESS(PIO_MDER_OFF) ///< Multi-driver enable register address.
#define PIOB_MDDR PIOB_ACCESS(PIO_MDDR_OFF) ///< Multi-driver disable register address.
#define PIOB_MDSR PIOB_ACCESS(PIO_MDSR_OFF) ///< Multi-driver status register address.
#endif /* PIO_HAS_MULTIDRIVER */
#if PIO_HAS_PULLUP
#define PIOB_PUDR PIOB_ACCESS(PIO_PUDR_OFF) ///< Pull-up disable register address.
#define PIOB_PUER PIOB_ACCESS(PIO_PUER_OFF) ///< Pull-up enable register address.
#define PIOB_PUSR PIOB_ACCESS(PIO_PUSR_OFF) ///< Pull-up status register address.
#endif /* PIO_HAS_PULLUP */
#if PIO_HAS_PERIPHERALSELECT
#define PIOB_ASR PIOB_ACCESS(PIO_ASR_OFF) ///< PIO peripheral A select register address.
#define PIOB_BSR PIOB_ACCESS(PIO_BSR_OFF) ///< PIO peripheral B select register address.
#define PIOB_ABSR PIOB_ACCESS(PIO_ABSR_OFF) ///< PIO peripheral AB status register address.
#endif /* PIO_HAS_PERIPHERALSELECT */
#if PIO_HAS_OUTPUTWRITEENABLE
#define PIOB_OWER PIOB_ACCESS(PIO_OWER_OFF) ///< PIO output write enable register address.
#define PIOB_OWDR PIOB_ACCESS(PIO_OWDR_OFF) ///< PIO output write disable register address.
#define PIOB_OWSR PIOB_ACCESS(PIO_OWSR_OFF) ///< PIO output write status register address.
#endif /* PIO_HAS_OUTPUTWRITEENABLE */
#endif /* PIOB_BASE */
/*\}*/
/** PIO C Register Addresses */
/*\{*/
#if defined(PIOC_BASE)
#define PIOC_ACCESS(offset) (*((reg32_t *)(PIOC_BASE + (offset))))
#define PIOC_PER PIOC_ACCESS(PIO_PER_OFF) ///< PIO enable register address.
#define PIOC_PDR PIOC_ACCESS(PIO_PDR_OFF) ///< PIO disable register address.
#define PIOC_PSR PIOC_ACCESS(PIO_PSR_OFF) ///< PIO status register address.
#define PIOC_OER PIOC_ACCESS(PIO_OER_OFF) ///< Output enable register address.
#define PIOC_ODR PIOC_ACCESS(PIO_ODR_OFF) ///< Output disable register address.
#define PIOC_OSR PIOC_ACCESS(PIO_OSR_OFF) ///< Output status register address.
#define PIOC_IFER PIOC_ACCESS(PIO_IFER_OFF) ///< Input filter enable register address.
#define PIOC_IFDR PIOC_ACCESS(PIO_IFDR_OFF) ///< Input filter disable register address.
#define PIOC_IFSR PIOC_ACCESS(PIO_IFSR_OFF) ///< Input filter status register address.
#define PIOC_SODR PIOC_ACCESS(PIO_SODR_OFF) ///< Set output data register address.
#define PIOC_CODR PIOC_ACCESS(PIO_CODR_OFF) ///< Clear output data register address.
#define PIOC_ODSR PIOC_ACCESS(PIO_ODSR_OFF) ///< Output data status register address.
#define PIOC_PDSR PIOC_ACCESS(PIO_PDSR_OFF) ///< Pin data status register address.
#define PIOC_IER PIOC_ACCESS(PIO_IER_OFF) ///< Interrupt enable register address.
#define PIOC_IDR PIOC_ACCESS(PIO_IDR_OFF) ///< Interrupt disable register address.
#define PIOC_IMR PIOC_ACCESS(PIO_IMR_OFF) ///< Interrupt mask register address.
#define PIOC_ISR PIOC_ACCESS(PIO_ISR_OFF) ///< Interrupt status register address.
#if PIO_HAS_MULTIDRIVER
#define PIOC_MDER PIOC_ACCESS(PIO_MDER_OFF) ///< Multi-driver enable register address.
#define PIOC_MDDR PIOC_ACCESS(PIO_MDDR_OFF) ///< Multi-driver disable register address.
#define PIOC_MDSR PIOC_ACCESS(PIO_MDSR_OFF) ///< Multi-driver status register address.
#endif /* PIO_HAS_MULTIDRIVER */
#if PIO_HAS_PULLUP
#define PIOC_PUDR PIOC_ACCESS(PIO_PUDR_OFF) ///< Pull-up disable register address.
#define PIOC_PUER PIOC_ACCESS(PIO_PUER_OFF) ///< Pull-up enable register address.
#define PIOC_PUSR PIOC_ACCESS(PIO_PUSR_OFF) ///< Pull-up status register address.
#endif /* PIO_HAS_PULLUP */
#if PIO_HAS_PERIPHERALSELECT
#define PIOC_ASR PIOC_ACCESS(PIO_ASR_OFF) ///< PIO peripheral A select register address.
#define PIOC_BSR PIOC_ACCESS(PIO_BSR_OFF) ///< PIO peripheral B select register address.
#define PIOC_ABSR PIOC_ACCESS(PIO_ABSR_OFF) ///< PIO peripheral AB status register address.
#endif /* PIO_HAS_PERIPHERALSELECT */
#if PIO_HAS_OUTPUTWRITEENABLE
#define PIOC_OWER PIOC_ACCESS(PIO_OWER_OFF) ///< PIO output write enable register address.
#define PIOC_OWDR PIOC_ACCESS(PIO_OWDR_OFF) ///< PIO output write disable register address.
#define PIOC_OWSR PIOC_ACCESS(PIO_OWSR_OFF) ///< PIO output write status register address.
#endif /* PIO_HAS_OUTPUTWRITEENABLE */
#endif /* PIOC_BASE */
/*\}*/
#endif /* AT91_PIO_H */

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/**
* \file
* <!--
* This file is part of BeRTOS.
*
* Bertos is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* As a special exception, you may use this file as part of a free software
* library without restriction. Specifically, if other files instantiate
* templates or use macros or inline functions from this file, or you compile
* this file and link it with other files to produce an executable, this
* file does not by itself cause the resulting executable to be covered by
* the GNU General Public License. This exception does not however
* invalidate any other reasons why the executable file might be covered by
* the GNU General Public License.
*
* Copyright 2007 Develer S.r.l. (http://www.develer.com/)
*
* -->
*
*
* \author Francesco Sacchi <batt@develer.com>
*
* AT91 periodic interval timer.
* This file is based on NUT/OS implementation. See license below.
*/
/*
* Copyright (C) 2007 by egnite Software GmbH. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
* SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* For additional information see http://www.ethernut.de/
*/
#ifndef AT91_PIT_H
#define AT91_PIT_H
#include <cfg/compiler.h>
/**
*Periodic Inverval Timer Mode Register
*\{
*/
#define PIT_MR_OFF 0x00000000 ///< Mode register offset.
#define PIT_MR (*((reg32_t *)(PIT_BASE + PIT_MR_OFF))) ///< Mode register address.
#define PIV_MASK 0x000FFFFF ///< Periodic interval value mask.
#define PIV_SHIFT 0 ///< Periodic interval value shift.
#define PITEN 24 ///< Periodic interval timer enable.
#define PITIEN 25 ///< Periodic interval timer interrupt enable.
/*\}*/
/**
* Periodic Inverval Timer Status Register
*\{
*/
#define PIT_SR_OFF 0x00000004 ///< Status register offset.
#define PIT_SR (*((reg32_t *)(PIT_BASE + PIT_SR_OFF))) ///< Status register address.
#define PITS 0 ///< Timer has reached PIV.
/*\}*/
/**
* Periodic Inverval Timer Value and Image Registers
*\{
*/
#define PIVR_OFF 0x00000008 ///< Value register offset.
#define PIVR (*((reg32_t *)(PIT_BASE + PIVR_OFF))) ///< Value register address.
#define PIIR_OFF 0x0000000C ///< Image register offset.
#define PIIR (*((reg32_t *)(PIT_BASE + PIIR_OFF))) ///< Image register address.
#define CPIV_MASK 0x000FFFFF ///< Current periodic interval value mask.
#define CPIV_SHIFT 0 ///< Current periodic interval value SHIFT.
#define PICNT_MASK 0xFFF00000 ///< Periodic interval counter mask.
#define PICNT_SHIFT 20 ///< Periodic interval counter LSB.
/*\}*/
#endif /* AT91_PIT_H */

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/**
* \file
* <!--
* This file is part of BeRTOS.
*
* Bertos is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* As a special exception, you may use this file as part of a free software
* library without restriction. Specifically, if other files instantiate
* templates or use macros or inline functions from this file, or you compile
* this file and link it with other files to produce an executable, this
* file does not by itself cause the resulting executable to be covered by
* the GNU General Public License. This exception does not however
* invalidate any other reasons why the executable file might be covered by
* the GNU General Public License.
*
* Copyright 2007 Develer S.r.l. (http://www.develer.com/)
*
* -->
*
*
* \author Francesco Sacchi <batt@develer.com>
*
* AT91 power management controller.
* This file is based on NUT/OS implementation. See license below.
*/
/*
* Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
* SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* For additional information see http://www.ethernut.de/
*/
#ifndef AT91_PMC_H
#define AT91_PMC_H
/** System Clock Enable, Disable and Status Register */
/*\{*/
#define PMC_SCER_OFF 0x00000000 ///< System clock enable register offset.
#define PMC_SCER (*((reg32_t *)(PMC_BASE + PMC_SCER_OFF))) ///< System clock enable register address.
#define PMC_SCDR_OFF 0x00000004 ///< System clock disable register offset.
#define PMC_SCDR (*((reg32_t *)(PMC_BASE + PMC_SCDR_OFF))) ///< System clock disable register address.
#define PMC_SCSR_OFF 0x00000008 ///< System clock status register offset.
#define PMC_SCSR (*((reg32_t *)(PMC_BASE + PMC_SCSR_OFF))) ///< System clock status register address.
#define PMC_PCK 0 ///< Processor clock.
#define PMC_UDP 7 ///< USB device port clock.
#define PMC_PCK0 8 ///< Programmable clock 0 output.
#define PMC_PCK1 9 ///< Programmable clock 1 output.
#define PMC_PCK2 10 ///< Programmable clock 2 output.
/*\}*/
/** Peripheral Clock Enable, Disable and Status Register */
/*\{*/
#define PMC_PCER_OFF 0x00000010 ///< Peripheral clock enable register offset.
#define PMC_PCER (*((reg32_t *)(PMC_BASE + PMC_PCER_OFF))) ///< Peripheral clock enable register address.
#define PMC_PCDR_OFF 0x00000014 ///< Peripheral clock disable register offset.
#define PMC_PCDR (*((reg32_t *)(PMC_BASE + PMC_PCDR_OFF))) ///< Peripheral clock disable register address.
#define PMC_PCSR_OFF 0x00000018 ///< Peripheral clock status register offset.
#define PMC_PCSR (*((reg32_t *)(PMC_BASE + PMC_PCSR_OFF))) ///< Peripheral clock status register address.
/*\}*/
/** Clock Generator Main Oscillator Register */
/*\{*/
#define CKGR_MOR_OFF 0x00000020 ///< Main oscillator register offset.
#define CKGR_MOR (*((reg32_t *)(PMC_BASE + CKGR_MOR_OFF))) ///< Main oscillator register address.
#define CKGR_MOSCEN 0 ///< Main oscillator enable.
#define CKGR_OSCBYPASS 1 ///< Main oscillator bypass.
#define CKGR_OSCOUNT_MASK 0x0000FF00 ///< Main oscillator start-up time mask.
#define CKGR_OSCOUNT_SHIFT 8 ///< Main oscillator start-up time LSB.
/*\}*/
/** Clock Generator Main Clock Frequency Register */
/*\{*/
#define CKGR_MCFR_OFF 0x00000024 ///< Main clock frequency register offset.
#define CKGR_MCFR (*((reg32_t *)(PMC_BASE + CKGR_MCFR_OFF))) ///< Main clock frequency register address.
#define CKGR_MAINF_MASK 0x0000FFFF ///< Main clock frequency mask mask.
#define CKGR_MAINRDY 16 ///< Main clock ready.
/*\}*/
/** PLL Registers */
/*\{*/
#define CKGR_PLLR_OFF 0x0000002C ///< Clock generator PLL register offset.
#define CKGR_PLLR (*((reg32_t *)(PMC_BASE + CKGR_PLLR_OFF))) ///< Clock generator PLL register address.
#define CKGR_DIV_MASK 0x000000FF ///< Divider.
#define CKGR_DIV_SHIFT 0 ///< Least significant bit of the divider.
#define CKGR_DIV_0 0x00000000 ///< Divider output is 0.
#define CKGR_DIV_BYPASS 0x00000001 ///< Divider is bypassed.
#define CKGR_PLLCOUNT_MASK 0x00003F00 ///< PLL counter mask.
#define CKGR_PLLCOUNT_SHIFT 8 ///< PLL counter LSB.
#define CKGR_OUT_MASK 0x0000C000 ///< PLL output frequency range.
#define CKGR_OUT_0 0x00000000 ///< Please refer to the PLL datasheet.
#define CKGR_OUT_1 0x00004000 ///< Please refer to the PLL datasheet.
#define CKGR_OUT_2 0x00008000 ///< Please refer to the PLL datasheet.
#define CKGR_OUT_3 0x0000C000 ///< Please refer to the PLL datasheet.
#define CKGR_MUL_MASK 0x07FF0000 ///< PLL multiplier.
#define CKGR_MUL_SHIFT 16 ///< Least significant bit of the PLL multiplier.
#define CKGR_USBDIV_MASK 0x30000000 ///< Divider for USB clocks.
#define CKGR_USBDIV_1 0x00000000 ///< Divider output is PLL clock output.
#define CKGR_USBDIV_2 0x10000000 ///< Divider output is PLL clock output divided by 2.
#define CKGR_USBDIV_4 0x20000000 ///< Divider output is PLL clock output divided by 4.
/*\}*/
/** Master Clock Register */
/*\{*/
#define PMC_MCKR_OFF 0x00000030 ///< Master clock register offset.
#define PMC_MCKR (*((reg32_t *)(PMC_BASE + PMC_MCKR_OFF))) ///< Master clock register address.
#define PMC_PCKR0_OFF 0x00000040 ///< Programmable clock 0 register offset.
#define PMC_PCKR0 (*((reg32_t *)(PMC_BASE + PMC_PCKR0_OFF))) ///< Programmable clock 0 register address.
#define PMC_PCKR1_OFF 0x00000044 ///< Programmable clock 1 register offset.
#define PMC_PCKR1 (*((reg32_t *)(PMC_BASE + PMC_PCKR1_OFF))) ///< Programmable clock 1 register address.
#define PMC_PCKR2_OFF 0x00000048 ///< Programmable clock 2 register offset.
#define PMC_PCKR2 (*((reg32_t *)(PMC_BASE + PMC_PCKR2_OFF))) ///< Programmable clock 2 register address.
#define PMC_CSS_MASK 0x00000003 ///< Clock selection mask.
#define PMC_CSS_SLOW_CLK 0x00000000 ///< Slow clock selected.
#define PMC_CSS_MAIN_CLK 0x00000001 ///< Main clock selected.
#define PMC_CSS_PLL_CLK 0x00000003 ///< PLL clock selected.
#define PMC_PRES_MASK 0x0000001C ///< Clock prescaler mask.
#define PMC_PRES_SHIFT 2 ///< Clock prescaler LSB.
#define PMC_PRES_CLK 0x00000000 ///< Selected clock, not divided.
#define PMC_PRES_CLK_2 0x00000004 ///< Selected clock divided by 2.
#define PMC_PRES_CLK_4 0x00000008 ///< Selected clock divided by 4.
#define PMC_PRES_CLK_8 0x0000000C ///< Selected clock divided by 8.
#define PMC_PRES_CLK_16 0x00000010 ///< Selected clock divided by 16.
#define PMC_PRES_CLK_32 0x00000014 ///< Selected clock divided by 32.
#define PMC_PRES_CLK_64 0x00000018 ///< Selected clock divided by 64.
/*\}*/
/** Power Management Status and Interrupt Registers */
/*\{*/
#define PMC_IER_OFF 0x00000060 ///< Interrupt enable register offset.
#define PMC_IER (*((reg32_t *)(PMC_BASE + PMC_IER_OFF))) ///< Interrupt enable register address.
#define PMC_IDR_OFF 0x00000064 ///< Interrupt disable register offset.
#define PMC_IDR (*((reg32_t *)(PMC_BASE + PMC_IDR_OFF))) ///< Interrupt disable register address.
#define PMC_SR_OFF 0x00000068 ///< Status register offset.
#define PMC_SR (*((reg32_t *)(PMC_BASE + PMC_SR_OFF))) ///< Status register address.
#define PMC_IMR_OFF 0x0000006C ///< Interrupt mask register offset.
#define PMC_IMR (*((reg32_t *)(PMC_BASE + PMC_IMR_OFF))) ///< Interrupt mask register address.
#define PMC_MOSCS 0 ///< Main oscillator.
#define PMC_LOCK 2 ///< PLL lock.
#define PMC_MCKRDY 3 ///< Master clock ready.
#define PMC_PCKRDY0 8 ///< Programmable clock 0 ready.
#define PMC_PCKRDY1 9 ///< Programmable clock 1 ready.
#define PMC_PCKRDY2 10 ///< Programmable clock 2 ready.
/*\}*/
#endif /* AT91_PMC_H */

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/**
* \file
* <!--
* This file is part of BeRTOS.
*
* Bertos is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* As a special exception, you may use this file as part of a free software
* library without restriction. Specifically, if other files instantiate
* templates or use macros or inline functions from this file, or you compile
* this file and link it with other files to produce an executable, this
* file does not by itself cause the resulting executable to be covered by
* the GNU General Public License. This exception does not however
* invalidate any other reasons why the executable file might be covered by
* the GNU General Public License.
*
* Copyright 2008 Develer S.r.l. (http://www.develer.com/)
*
* -->
*
*
* \author Francesco Sacchi <batt@develer.com>
*
* AT91SAM7 Pulse Width Modulation Controller.
*/
#ifndef AT91_PWM_H
#define AT91_PWM_H
/**
* PWM Mode Register.
*/
/*\{*/
#define PWM_MR_OFF 0x00000000 ///< PWM Mode Register offset.
#define PWM_MR (*((reg32_t *)(PWMC_BASE + PWM_MR_OFF))) ///< PWM Mode Register.
#define PWM_MR_DIVA_MASK 0x000000FF ///< PWM Mode Divide factor A Mask.
#define PWM_MR_DIVA_SHIFT 0 ///< PWM Mode Divide factor A LSB.
#define PWM_MR_DIVB_MASK 0x00FF0000 ///< PWM Mode Divide factor B Mask.
#define PWM_MR_DIVB_SHIFT 16 ///< PWM Mode Divide factor B LSB.
#define PWM_MR_PREA_MASK 0x00000F00 ///< PWM Mode prescaler A Mask.
#define PWM_MR_PREA_SHIFT 8 ///< PWM Mode prescaler A LSB.
#define PWM_MR_PREB_MASK 0x0F000000 ///< PWM Mode prescaler B Mask.
#define PWM_MR_PREB_SHIFT 24 ///< PWM Mode prescaler B LSB.
#define PWM_MR_PRE_MCK 0 ///< PWM Mode prescaler set to MCK.
#define PWM_MR_PRE_MCK_DIV2 1 ///< PWM Mode prescaler set to MCK/2.
#define PWM_MR_PRE_MCK_DIV4 2 ///< PWM Mode prescaler set to MCK/4.
#define PWM_MR_PRE_MCK_DIV8 3 ///< PWM Mode prescaler set to MCK/8.
#define PWM_MR_PRE_MCK_DIV16 4 ///< PWM Mode prescaler set to MCK/16.
#define PWM_MR_PRE_MCK_DIV32 5 ///< PWM Mode prescaler set to MCK/32.
#define PWM_MR_PRE_MCK_DIV64 6 ///< PWM Mode prescaler set to MCK/64.
#define PWM_MR_PRE_MCK_DIV128 7 ///< PWM Mode prescaler set to MCK/128.
#define PWM_MR_PRE_MCK_DIV256 8 ///< PWM Mode prescaler set to MCK/256.
#define PWM_MR_PRE_MCK_DIV512 9 ///< PWM Mode prescaler set to MCK/512.
#define PWM_MR_PRE_MCK_DIV1024 10 ///< PWM Mode prescaler set to MCK/1024.
/*\}*/
/**
* PWM Channel IDs.
*/
/*\{*/
#define PWM_CHID_MASK 0x0000000F
#define PWM_CHID0 0
#define PWM_CHID1 1
#define PWM_CHID2 2
#define PWM_CHID3 3
/*\}*/
/**
* PWM Enable Register.
*/
/*\{*/
#define PWM_ENA_OFF 0x00000004 ///< PWM Enable Register offset.
#define PWM_ENA (*((reg32_t *)(PWMC_BASE + PWM_ENA_OFF))) ///< PWM Enable Register.
/*\}*/
/**
* PWM Disable Register.
*/
/*\{*/
#define PWM_DIS_OFF 0x00000008 ///< PWM Disable Register offset.
#define PWM_DIS (*((reg32_t *)(PWMC_BASE + PWM_DIS_OFF))) ///< PWM Disable Register.
/*\}*/
/**
* PWM Status Register.
*/
/*\{*/
#define PWM_SR_OFF 0x0000000C ///< PWM Status Register offset.
#define PWM_SR (*((reg32_t *)(PWMC_BASE + PWM_SR_OFF))) ///< PWM Status Register.
/*\}*/
/**
* PWM Interrupt Enable Register.
*/
/*\{*/
#define PWM_IER_OFF 0x00000010 ///< PWM Interrupt Enable Register offset.
#define PWM_IER (*((reg32_t *)(PWMC_BASE + PWM_IER_OFF))) ///< PWM Interrupt Enable Register.
/*\}*/
/**
* PWM Interrupt Disable Register.
*/
/*\{*/
#define PWM_IDR_OFF 0x00000014 ///< PWM Interrupt Disable Register offset.
#define PWM_IDR (*((reg32_t *)(PWMC_BASE + PWM_IDR_OFF))) ///< PWM Interrupt Disable Register.
/*\}*/
/**
* PWM Interrupt Mask Register.
*/
/*\{*/
#define PWM_IMR_OFF 0x00000018 ///< PWM Interrupt Mask Register offset.
#define PWM_IMR (*((reg32_t *)(PWMC_BASE + PWM_IMR_OFF))) ///< PWM Interrupt Mask Register.
/*\}*/
/**
* PWM Interrupt Status Register.
*/
/*\{*/
#define PWM_ISR_OFF 0x0000001C ///< PWM Interrupt Status Register offset.
#define PWM_ISR (*((reg32_t *)(PWMC_BASE + PWM_ISR_OFF))) ///< PWM Interrupt Status Register.
/*\}*/
#define PWM_CH0_OFF 0x00000200 ///< PWM Channel 0 registers offset.
#define PWM_CH1_OFF 0x00000220 ///< PWM Channel 1 registers offset.
#define PWM_CH2_OFF 0x00000240 ///< PWM Channel 2 registers offset.
#define PWM_CH3_OFF 0x00000260 ///< PWM Channel 3 registers offset.
/**
* PWM Channel Mode Register.
*/
/*\{*/
#define PWM_CMR_OFF 0x00000000 ///< PWM Channel Mode Register offset.
#define PWM_CMR0 (*((reg32_t *)(PWMC_BASE + PWM_CMR_OFF + PWM_CH0_OFF))) ///< PWM Channel 0 Mode Register.
#define PWM_CMR1 (*((reg32_t *)(PWMC_BASE + PWM_CMR_OFF + PWM_CH1_OFF))) ///< PWM Channel 1 Mode Register.
#define PWM_CMR2 (*((reg32_t *)(PWMC_BASE + PWM_CMR_OFF + PWM_CH2_OFF))) ///< PWM Channel 2 Mode Register.
#define PWM_CMR3 (*((reg32_t *)(PWMC_BASE + PWM_CMR_OFF + PWM_CH3_OFF))) ///< PWM Channel 3 Mode Register.
#define PWM_CPRE_MCK_MASK 0x0000000F ///< PWM Mode prescaler mask.
#define PWM_CPRE_MCK 0 ///< PWM Mode prescaler set to MCK.
#define PWM_CPRE_MCK_DIV2 1 ///< PWM Mode prescaler set to MCK/2.
#define PWM_CPRE_MCK_DIV4 2 ///< PWM Mode prescaler set to MCK/4.
#define PWM_CPRE_MCK_DIV8 3 ///< PWM Mode prescaler set to MCK/8.
#define PWM_CPRE_MCK_DIV16 4 ///< PWM Mode prescaler set to MCK/16.
#define PWM_CPRE_MCK_DIV32 5 ///< PWM Mode prescaler set to MCK/32.
#define PWM_CPRE_MCK_DIV64 6 ///< PWM Mode prescaler set to MCK/64.
#define PWM_CPRE_MCK_DIV128 7 ///< PWM Mode prescaler set to MCK/128.
#define PWM_CPRE_MCK_DIV256 8 ///< PWM Mode prescaler set to MCK/256.
#define PWM_CPRE_MCK_DIV512 9 ///< PWM Mode prescaler set to MCK/512.
#define PWM_CPRE_MCK_DIV1024 10 ///< PWM Mode prescaler set to MCK/1024.
#define PWM_CPRE_CLKA 11 ///< PWM Mode prescaler set to CLKA.
#define PWM_CPRE_CLKB 12 ///< PWM Mode prescaler set to CLKB.
#define PWM_CALG 8 ///< PWM Mode channel alignment.
#define PWM_CPOL 9 ///< PWM Mode channel polarity.
#define PWM_CPD 10 ///< PWM Mode channel update period.
/*\}*/
/**
* PWM Channel Duty Cycle Register.
*/
/*\{*/
#define PWM_CDTY_OFF 0x00000004 ///< PWM Channel Duty Cycle Register offset.
#define PWM_CDTY0 (*((reg32_t *)(PWMC_BASE + PWM_CDTY_OFF + PWM_CH0_OFF))) ///< PWM Channel 0 Duty Cycle Register.
#define PWM_CDTY1 (*((reg32_t *)(PWMC_BASE + PWM_CDTY_OFF + PWM_CH1_OFF))) ///< PWM Channel 1 Duty Cycle Register.
#define PWM_CDTY2 (*((reg32_t *)(PWMC_BASE + PWM_CDTY_OFF + PWM_CH2_OFF))) ///< PWM Channel 2 Duty Cycle Register.
#define PWM_CDTY3 (*((reg32_t *)(PWMC_BASE + PWM_CDTY_OFF + PWM_CH3_OFF))) ///< PWM Channel 3 Duty Cycle Register.
/*\}*/
/**
* PWM Channel Period Register.
*/
/*\{*/
#define PWM_CPRD_OFF 0x00000008 ///< PWM Channel Period Register offset.
#define PWM_CPRD0 (*((reg32_t *)(PWMC_BASE + PWM_CPRD_OFF + PWM_CH0_OFF))) ///< PWM Channel 0 Period Register.
#define PWM_CPRD1 (*((reg32_t *)(PWMC_BASE + PWM_CPRD_OFF + PWM_CH1_OFF))) ///< PWM Channel 1 Period Register.
#define PWM_CPRD2 (*((reg32_t *)(PWMC_BASE + PWM_CPRD_OFF + PWM_CH2_OFF))) ///< PWM Channel 2 Period Register.
#define PWM_CPRD3 (*((reg32_t *)(PWMC_BASE + PWM_CPRD_OFF + PWM_CH3_OFF))) ///< PWM Channel 3 Period Register.
/*\}*/
/**
* PWM Channel Counter Register.
*/
/*\{*/
#define PWM_CCNT_OFF 0x0000000C ///< PWM Channel Counter Register offset.
#define PWM_CCNT0 (*((reg32_t *)(PWMC_BASE + PWM_CCNT_OFF + PWM_CH0_OFF))) ///< PWM Channel 0 Counter Register.
#define PWM_CCNT1 (*((reg32_t *)(PWMC_BASE + PWM_CCNT_OFF + PWM_CH1_OFF))) ///< PWM Channel 1 Counter Register.
#define PWM_CCNT2 (*((reg32_t *)(PWMC_BASE + PWM_CCNT_OFF + PWM_CH2_OFF))) ///< PWM Channel 2 Counter Register.
#define PWM_CCNT3 (*((reg32_t *)(PWMC_BASE + PWM_CCNT_OFF + PWM_CH3_OFF))) ///< PWM Channel 3 Counter Register.
/*\}*/
/**
* PWM Channel Update Register.
*/
/*\{*/
#define PWM_CUPD_OFF 0x00000010 ///< PWM Channel Update Register offset.
#define PWM_CUPD0 (*((reg32_t *)(PWMC_BASE + PWM_CUPD_OFF + PWM_CH0_OFF))) ///< PWM Channel 0 Update Register.
#define PWM_CUPD1 (*((reg32_t *)(PWMC_BASE + PWM_CUPD_OFF + PWM_CH1_OFF))) ///< PWM Channel 1 Update Register.
#define PWM_CUPD2 (*((reg32_t *)(PWMC_BASE + PWM_CUPD_OFF + PWM_CH2_OFF))) ///< PWM Channel 2 Update Register.
#define PWM_CUPD3 (*((reg32_t *)(PWMC_BASE + PWM_CUPD_OFF + PWM_CH3_OFF))) ///< PWM Channel 3 Update Register.
/*\}*/
#endif /* AT91_PWM_H */

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/**
* \file
* <!--
* This file is part of BeRTOS.
*
* Bertos is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* As a special exception, you may use this file as part of a free software
* library without restriction. Specifically, if other files instantiate
* templates or use macros or inline functions from this file, or you compile
* this file and link it with other files to produce an executable, this
* file does not by itself cause the resulting executable to be covered by
* the GNU General Public License. This exception does not however
* invalidate any other reasons why the executable file might be covered by
* the GNU General Public License.
*
* Copyright 2007 Develer S.r.l. (http://www.develer.com/)
*
* -->
*
*
* \author Francesco Sacchi <batt@develer.com>
*
* AT91 reset controller.
* This file is based on NUT/OS implementation. See license below.
*/
/*
* Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
* SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* For additional information see http://www.ethernut.de/
*/
#ifndef AT91_RTSC_H
#define AT91_RTSC_H
/** Reset Controller Control Register */
/*\{*/
#define RSTC_CR (*((reg32_t *)(RSTC_BASE + 0x00))) ///< Reset controller control register address.
#define RSTC_PROCRST 0 ///< Processor reset.
#define RSTC_PERRST 2 ///< Peripheral reset.
#define RSTC_EXTRST 3 ///< External reset.
#define RSTC_KEY 0xA5000000 ///< Password.
/*\}*/
/** Reset Controller Status Register */
/*\{*/
#define RSTC_SR (*((reg32_t *)(RSTC_BASE + 0x04))) ///< Reset controller status register address.
#define RSTC_URSTS 0 ///< User reset status.
#define RSTC_BODSTS 1 ///< Brownout detection status.
#define RSTC_RSTTYP_MASK 0x00000700 ///< Reset type.
#define RSTC_RSTTYP_POWERUP 0x00000000 ///< Power-up reset.
//#define RSTC_RSTTYP_WAKEUP 0x00000100 ///< VDDCORE rising.
#define RSTC_RSTTYP_WATCHDOG 0x00000200 ///< Watchdog reset.
#define RSTC_RSTTYP_SOFTWARE 0x00000300 ///< Software reset.
#define RSTC_RSTTYP_USER 0x00000400 ///< User reset.
#define RSTC_RSTTYP_BROWNOUT 0x00000500 ///< Brownout reset.
#define RSTC_NRSTL 16 ///< NRST pin level.
#define RSTC_SRCMP 17 ///< Software reset command in progress.
/*\}*/
/** Reset Controller Mode Register */
/*\{*/
#define RSTC_MR (*((reg32_t *)(RSTC_BASE + 0x08))) ///< Reset controller mode register address.
#define RSTC_URSTEN 0 ///< User reset enable.
#define RSTC_URSTIEN 4 ///< User reset interrupt enable.
#define RSTC_ERSTL_MASK 0x00000F00 ///< External reset length.
#define RSTC_ERSTL_SHIFT 8 ///< Least significant bit of external reset length.
#define RSTC_BODIEN 16 ///< Brown-out detection interrupt enable.
/*\}*/
#endif /* AT91_RTSC_H */

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/**
* \file
* <!--
* This file is part of BeRTOS.
*
* Bertos is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* As a special exception, you may use this file as part of a free software
* library without restriction. Specifically, if other files instantiate
* templates or use macros or inline functions from this file, or you compile
* this file and link it with other files to produce an executable, this
* file does not by itself cause the resulting executable to be covered by
* the GNU General Public License. This exception does not however
* invalidate any other reasons why the executable file might be covered by
* the GNU General Public License.
*
* Copyright 2007 Develer S.r.l. (http://www.develer.com/)
*
* -->
*
*
* \author Francesco Sacchi <batt@develer.com>
*
* AT91SAM7 SPI register definitions.
* This file is based on NUT/OS implementation. See license below.
*/
/*
* Copyright (C) 2006-2007 by egnite Software GmbH. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
* SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* For additional information see http://www.ethernut.de/
*/
#ifndef AT91_SPI_H
#define AT91_SPI_H
/**
* SPI Control Register
*/
/*\{*/
#define SPI_CR_OFF 0x00000000 ///< Control register offset.
#define SPI_SPIEN 0 ///< SPI enable.
#define SPI_SPIDIS 1 ///< SPI disable.
#define SPI_SWRST 7 ///< Software reset.
#define SPI_LASTXFER 24 ///< Last transfer.
/*\}*/
/**
* SPI Mode Register
*/
/*\{*/
#define SPI_MR_OFF 0x00000004 ///< Mode register offset.
#define SPI_MSTR 0 ///< Master mode.
#define SPI_PS 1 ///< Peripheral select.
#define SPI_PCSDEC 2 ///< Chip select decode.
#define SPI_FDIV 3 ///< Clock selection.
#define SPI_MODFDIS 4 ///< Mode fault detection.
#define SPI_LLB 7 ///< Local loopback enable.
#define SPI_PCS 0x000F0000 ///< Peripheral chip select mask.
#define SPI_PCS_0 0x000E0000 ///< Peripheral chip select 0.
#define SPI_PCS_1 0x000D0000 ///< Peripheral chip select 1.
#define SPI_PCS_2 0x000B0000 ///< Peripheral chip select 2.
#define SPI_PCS_3 0x00070000 ///< Peripheral chip select 3.
#define SPI_PCS_SHIFT 16 ///< Least significant bit of peripheral chip select.
#define SPI_DLYBCS 0xFF000000 ///< Mask for delay between chip selects.
#define SPI_DLYBCS_SHIFT 24 ///< Least significant bit of delay between chip selects.
/*\}*/
/**
* SPI Receive Data Register
*/
/*\{*/
#define SPI_RDR_OFF 0x00000008 ///< Receive data register offset.
#define SPI_RD 0x0000FFFF ///< Receive data mask.
#define SPI_RD_SHIFT 0 ///< Least significant bit of receive data.
/*\}*/
/**
* SPI Transmit Data Register
*/
/*\{*/
#define SPI_TDR_OFF 0x0000000C ///< Transmit data register offset.
#define SPI_TD 0x0000FFFF ///< Transmit data mask.
#define SPI_TD_SHIFT 0 ///< Least significant bit of transmit data.
/*\}*/
/**
* SPI Status and Interrupt Register
*/
/*\{*/
#define SPI_SR_OFF 0x00000010 ///< Status register offset.
#define SPI_IER_OFF 0x00000014 ///< Interrupt enable register offset.
#define SPI_IDR_OFF 0x00000018 ///< Interrupt disable register offset.
#define SPI_IMR_OFF 0x0000001C ///< Interrupt mask register offset.
#define SPI_RDRF 0 ///< Receive data register full.
#define SPI_TDRE 1 ///< Transmit data register empty.
#define SPI_MODF 2 ///< Mode fault error.
#define SPI_OVRES 3 ///< Overrun error status.
#define SPI_ENDRX 4 ///< End of RX buffer.
#define SPI_ENDTX 5 ///< End of TX buffer.
#define SPI_RXBUFF 6 ///< RX buffer full.
#define SPI_TXBUFE 7 ///< TX buffer empty.
#define SPI_NSSR 8 ///< NSS rising.
#define SPI_TXEMPTY 9 ///< Transmission register empty.
#define SPI_SPIENS 16 ///< SPI enable status.
/*\}*/
/**
* SPI Chip Select Registers
*/
/*\{*/
#define SPI_CSR0_OFF 0x00000030 ///< Chip select register 0 offset.
#define SPI_CSR1_OFF 0x00000034 ///< Chip select register 1 offset.
#define SPI_CSR2_OFF 0x00000038 ///< Chip select register 2 offset.
#define SPI_CSR3_OFF 0x0000003C ///< Chip select register 3 offset.
#define SPI_CPOL 0 ///< Clock polarity.
#define SPI_NCPHA 1 ///< Clock phase.
#define SPI_CSAAT 3 ///< Chip select active after transfer.
#define SPI_BITS 0x000000F0 ///< Bits per transfer mask.
#define SPI_BITS_8 0x00000000 ///< 8 bits per transfer.
#define SPI_BITS_9 0x00000010 ///< 9 bits per transfer.
#define SPI_BITS_10 0x00000020 ///< 10 bits per transfer.
#define SPI_BITS_11 0x00000030 ///< 11 bits per transfer.
#define SPI_BITS_12 0x00000040 ///< 12 bits per transfer.
#define SPI_BITS_13 0x00000050 ///< 13 bits per transfer.
#define SPI_BITS_14 0x00000060 ///< 14 bits per transfer.
#define SPI_BITS_15 0x00000070 ///< 15 bits per transfer.
#define SPI_BITS_16 0x00000080 ///< 16 bits per transfer.
#define SPI_BITS_SHIFT 4 ///< Least significant bit of bits per transfer.
#define SPI_SCBR 0x0000FF00 ///< Serial clock baud rate mask.
#define SPI_SCBR_SHIFT 8 ///< Least significant bit of serial clock baud rate.
#define SPI_DLYBS 0x00FF0000 ///< Delay before SPCK mask.
#define SPI_DLYBS_SHIFT 16 ///< Least significant bit of delay before SPCK.
#define SPI_DLYBCT 0xFF000000 ///< Delay between consecutive transfers mask.
#define SPI_DLYBCT_SHIFT 24 ///< Least significant bit of delay between consecutive transfers.
/*\}*/
/**
* Single SPI Register Addresses
*/
/*\{*/
#if defined(SPI_BASE)
#define SPI0_BASE SPI_BASE
#define SPI_CR SPI0_CR ///< SPI Control Register Write-only.
#define SPI_MR SPI0_MR ///< SPI Mode Register Read/Write Reset=0x0.
#define SPI_RDR SPI0_RDR ///< SPI Receive Data Register Read-only Reset=0x0.
#define SPI_TDR SPI0_TDR ///< SPI Transmit Data Register Write-only .
#define SPI_SR SPI0_SR ///< SPI Status Register Read-only Reset=0x000000F0.
#define SPI_IER SPI0_IER ///< SPI Interrupt Enable Register Write-only.
#define SPI_IDR SPI0_IDR ///< SPI Interrupt Disable Register Write-only.
#define SPI_IMR SPI0_IMR ///< SPI Interrupt Mask Register Read-only Reset=0x0.
#define SPI_CSR0 SPI0_CSR0 ///< SPI Chip Select Register 0 Read/Write Reset=0x0.
#define SPI_CSR1 SPI0_CSR1 ///< SPI Chip Select Register 1 Read/Write Reset=0x0.
#define SPI_CSR2 SPI0_CSR2 ///< SPI Chip Select Register 2 Read/Write Reset=0x0.
#define SPI_CSR3 SPI0_CSR3 ///< SPI Chip Select Register 3 Read/Write Reset=0x0.
#if defined(SPI_HAS_PDC)
#define SPI_RPR SPI0_RPR ///< PDC channel 0 receive pointer register.
#define SPI_RCR SPI0_RCR ///< PDC channel 0 receive counter register.
#define SPI_TPR SPI0_TPR ///< PDC channel 0 transmit pointer register.
#define SPI_TCR SPI0_TCR ///< PDC channel 0 transmit counter register.
#define SPI_RNPR SPI0_RNPR ///< PDC channel 0 receive next pointer register.
#define SPI_RNCR SPI0_RNCR ///< PDC channel 0 receive next counter register.
#define SPI_TNPR SPI0_TNPR ///< PDC channel 0 transmit next pointer register.
#define SPI_TNCR SPI0_TNCR ///< PDC channel 0 transmit next counter register.
#define SPI_PTCR SPI0_PTCR ///< PDC channel 0 transfer control register.
#define SPI_PTSR SPI0_PTSR ///< PDC channel 0 transfer status register.
#endif /* SPI_HAS_PDC */
#endif /* SPI_BASE */
/*\}*/
/**
* SPI 0 Register Addresses
*/
/*\{*/
#if defined(SPI0_BASE)
#define SPI0_CR (*((reg32_t *)(SPI0_BASE + SPI_CR_OFF))) ///< SPI Control Register Write-only.
#define SPI0_MR (*((reg32_t *)(SPI0_BASE + SPI_MR_OFF))) ///< SPI Mode Register Read/Write Reset=0x0.
#define SPI0_RDR (*((reg32_t *)(SPI0_BASE + SPI_RDR_OFF))) ///< SPI Receive Data Register Read-only Reset=0x0.
#define SPI0_TDR (*((reg32_t *)(SPI0_BASE + SPI_TDR_OFF))) ///< SPI Transmit Data Register Write-only .
#define SPI0_SR (*((reg32_t *)(SPI0_BASE + SPI_SR_OFF))) ///< SPI Status Register Read-only Reset=0x000000F0.
#define SPI0_IER (*((reg32_t *)(SPI0_BASE + SPI_IER_OFF))) ///< SPI Interrupt Enable Register Write-only.
#define SPI0_IDR (*((reg32_t *)(SPI0_BASE + SPI_IDR_OFF))) ///< SPI Interrupt Disable Register Write-only.
#define SPI0_IMR (*((reg32_t *)(SPI0_BASE + SPI_IMR_OFF))) ///< SPI Interrupt Mask Register Read-only Reset=0x0.
#define SPI0_CSR0 (*((reg32_t *)(SPI0_BASE + SPI_CSR0_OFF))) ///< SPI Chip Select Register 0 Read/Write Reset=0x0.
#define SPI0_CSR1 (*((reg32_t *)(SPI0_BASE + SPI_CSR1_OFF))) ///< SPI Chip Select Register 1 Read/Write Reset=0x0.
#define SPI0_CSR2 (*((reg32_t *)(SPI0_BASE + SPI_CSR2_OFF))) ///< SPI Chip Select Register 2 Read/Write Reset=0x0.
#define SPI0_CSR3 (*((reg32_t *)(SPI0_BASE + SPI_CSR3_OFF))) ///< SPI Chip Select Register 3 Read/Write Reset=0x0.
#if defined(SPI_HAS_PDC)
#define SPI0_RPR (*((reg32_t *)(SPI0_BASE + PERIPH_RPR_OFF))) ///< PDC channel 0 receive pointer register.
#define SPI0_RCR (*((reg32_t *)(SPI0_BASE + PERIPH_RCR_OFF))) ///< PDC channel 0 receive counter register.
#define SPI0_TPR (*((reg32_t *)(SPI0_BASE + PERIPH_TPR_OFF))) ///< PDC channel 0 transmit pointer register.
#define SPI0_TCR (*((reg32_t *)(SPI0_BASE + PERIPH_TCR_OFF))) ///< PDC channel 0 transmit counter register.
#define SPI0_RNPR (*((reg32_t *)(SPI0_BASE + PERIPH_RNPR_OFF))) ///< PDC channel 0 receive next pointer register.
#define SPI0_RNCR (*((reg32_t *)(SPI0_BASE + PERIPH_RNCR_OFF))) ///< PDC channel 0 receive next counter register.
#define SPI0_TNPR (*((reg32_t *)(SPI0_BASE + PERIPH_TNPR_OFF))) ///< PDC channel 0 transmit next pointer register.
#define SPI0_TNCR (*((reg32_t *)(SPI0_BASE + PERIPH_TNCR_OFF))) ///< PDC channel 0 transmit next counter register.
#define SPI0_PTCR (*((reg32_t *)(SPI0_BASE + PERIPH_PTCR_OFF))) ///< PDC channel 0 transfer control register.
#define SPI0_PTSR (*((reg32_t *)(SPI0_BASE + PERIPH_PTSR_OFF))) ///< PDC channel 0 transfer status register.
#endif /* SPI_HAS_PDC */
#endif /* SPI0_BASE */
/*\}*/
/**
* SPI 1 Register Addresses
*/
/*\{*/
#if defined(SPI1_BASE)
#define SPI1_CR (*((reg32_t *)(SPI1_BASE + SPI_CR_OFF))) ///< SPI Control Register Write-only.
#define SPI1_MR (*((reg32_t *)(SPI1_BASE + SPI_MR_OFF))) ///< SPI Mode Register Read/Write Reset=0x0.
#define SPI1_RDR (*((reg32_t *)(SPI1_BASE + SPI_RDR_OFF))) ///< SPI Receive Data Register Read-only Reset=0x0.
#define SPI1_TDR (*((reg32_t *)(SPI1_BASE + SPI_TDR_OFF))) ///< SPI Transmit Data Register Write-only .
#define SPI1_SR (*((reg32_t *)(SPI1_BASE + SPI_SR_OFF))) ///< SPI Status Register Read-only Reset=0x000000F0.
#define SPI1_IER (*((reg32_t *)(SPI1_BASE + SPI_IER_OFF))) ///< SPI Interrupt Enable Register Write-only.
#define SPI1_IDR (*((reg32_t *)(SPI1_BASE + SPI_IDR_OFF))) ///< SPI Interrupt Disable Register Write-only.
#define SPI1_IMR (*((reg32_t *)(SPI1_BASE + SPI_IMR_OFF))) ///< SPI Interrupt Mask Register Read-only Reset=0x0.
#define SPI1_CSR0 (*((reg32_t *)(SPI1_BASE + SPI_CSR0_OFF))) ///< SPI Chip Select Register 0 Read/Write Reset=0x0.
#define SPI1_CSR1 (*((reg32_t *)(SPI1_BASE + SPI_CSR1_OFF))) ///< SPI Chip Select Register 1 Read/Write Reset=0x0.
#define SPI1_CSR2 (*((reg32_t *)(SPI1_BASE + SPI_CSR2_OFF))) ///< SPI Chip Select Register 2 Read/Write Reset=0x0.
#define SPI1_CSR3 (*((reg32_t *)(SPI1_BASE + SPI_CSR3_OFF))) ///< SPI Chip Select Register 3 Read/Write Reset=0x0.
#if defined(SPI_HAS_PDC)
#define SPI1_RPR (*((reg32_t *)(SPI1_BASE + PERIPH_RPR_OFF))) ///< PDC channel 1 receive pointer register.
#define SPI1_RCR (*((reg32_t *)(SPI1_BASE + PERIPH_RCR_OFF))) ///< PDC channel 1 receive counter register.
#define SPI1_TPR (*((reg32_t *)(SPI1_BASE + PERIPH_TPR_OFF))) ///< PDC channel 1 transmit pointer register.
#define SPI1_TCR (*((reg32_t *)(SPI1_BASE + PERIPH_TCR_OFF))) ///< PDC channel 1 transmit counter register.
#define SPI1_RNPR (*((reg32_t *)(SPI1_BASE + PERIPH_RNPR_OFF))) ///< PDC channel 1 receive next pointer register.
#define SPI1_RNCR (*((reg32_t *)(SPI1_BASE + PERIPH_RNCR_OFF))) ///< PDC channel 1 receive next counter register.
#define SPI1_TNPR (*((reg32_t *)(SPI1_BASE + PERIPH_TNPR_OFF))) ///< PDC channel 1 transmit next pointer register.
#define SPI1_TNCR (*((reg32_t *)(SPI1_BASE + PERIPH_TNCR_OFF))) ///< PDC channel 1 transmit next counter register.
#define SPI1_PTCR (*((reg32_t *)(SPI1_BASE + PERIPH_PTCR_OFF))) ///< PDC channel 1 transfer control register.
#define SPI1_PTSR (*((reg32_t *)(SPI1_BASE + PERIPH_PTSR_OFF))) ///< PDC channel 1 transfer status register.
#endif /* SPI_HAS_PDC */
#endif /* SPI1_BASE */
/*\}*/
#endif /* AT91_SPI_H */

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/**
* \file
* <!--
* This file is part of BeRTOS.
*
* Bertos is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* As a special exception, you may use this file as part of a free software
* library without restriction. Specifically, if other files instantiate
* templates or use macros or inline functions from this file, or you compile
* this file and link it with other files to produce an executable, this
* file does not by itself cause the resulting executable to be covered by
* the GNU General Public License. This exception does not however
* invalidate any other reasons why the executable file might be covered by
* the GNU General Public License.
*
* Copyright 2009 Develer S.r.l. (http://www.develer.com/)
*
* -->
*
*
* \author Luca Ottaviano <lottaviano@develer.com>
*
* AT91SAM7 SSC register definitions.
* This file is based on NUT/OS implementation. See license below.
*/
/*
* Copyright (C) 2006-2007 by egnite Software GmbH. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
* SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* For additional information see http://www.ethernut.de/
*/
#ifndef AT91_SSC_H
#define AT91_SSC_H
#include <io/at91sam7.h>
/**
* SSC Control Register
*/
/*\{*/
#define SSC_CR_OFF 0x00000000 ///< Control register offset.
#define SSC_RXEN 0 ///< Receive enable.
#define SSC_RXDIS 1 ///< Receive disable.
#define SSC_TXEN 8 ///< Transmit enable.
#define SSC_TXDIS 9 ///< Transmit disable.
#define SSC_SWRST 15 ///< Software reset.
/*\}*/
/**
* SSC Clock Mode Register
*/
/*\{*/
#define SSC_CMR_OFF 0x00000004 ///< Clock mode register offset.
#define SSC_DIV_MASK 0x00000FFF ///< Clock divider.
/*\}*/
/**
* SSC Receive/Transmit Clock Mode Register
*/
/*\{*/
#define SSC_RCMR_OFF 0x00000010 ///< Receive clock mode register offset.
#define SSC_TCMR_OFF 0x00000018 ///< Transmit clock mode register offset.
#define SSC_CKS_MASK 0x00000003 ///< Receive clock selection.
#define SSC_CKS_DIV 0x00000000 ///< Divided clock.
#define SSC_CKS_CLK 0x00000001 ///< RK/TK clock signal.
#define SSC_CKS_PIN 0x00000002 ///< TK/RK pin.
#define SSC_CKO_MASK 0x0000001C ///< Receive clock output mode selection.
#define SSC_CKO_NONE 0x00000000 ///< None.
#define SSC_CKO_CONT 0x00000004 ///< Continous receive clock.
#define SSC_CKO_TRAN 0x00000008 ///< Receive clock only during data transfers.
#define SSC_CKI 5 ///< Receive clock inversion.
#define SSC_CKG_MASK 0x000000C0 ///< Receive clock gating selection.
#define SSC_CKG_NONE 0x00000000 ///< None, continous clock.
#define SSC_CKG_FL 0x00000040 ///< Continous receive clock.
#define SSC_CKG_FH 0x00000080 ///< Receive clock only during data transfers.
#define SSC_START_MASK 0x00000F00 ///< Receive start selection.
#define SSC_START_CONT 0x00000000 ///< Receive start as soon as enabled.
#define SSC_START_TX 0x00000100 ///< Receive start on transmit start.
#define SSC_START_RX 0x00000100 ///< Receive start on receive start.
#define SSC_START_LOW_F 0x00000200 ///< Receive start on low level RF.
#define SSC_START_HIGH_F 0x00000300 ///< Receive start on high level RF.
#define SSC_START_FALL_F 0x00000400 ///< Receive start on falling edge RF.
#define SSC_START_RISE_F 0x00000500 ///< Receive start on rising edge RF.
#define SSC_START_LEVEL_F 0x00000600 ///< Receive start on any RF level change.
#define SSC_START_EDGE_F 0x00000700 ///< Receive start on any RF edge.
#define SSC_START_COMP0 0x00000800 ///< Receive on compare 0.
#define SSC_STOP 12 ///< Receive stop selection.
#define SSC_STTDLY_MASK 0x00FF0000 ///< Receive start delay.
#define SSC_STTDLY_SHIFT 16 ///< Least significant bit of receive start delay.
#define SSC_PERIOD_MASK 0xFF000000 ///< Receive period divider selection.
#define SSC_PERIOD_SHIFT 24 ///< Least significant bit of receive period divider selection.
/*\}*/
/**
* SSC Receive/Transmit Frame Mode Registers
*/
/*\{*/
#define SSC_RFMR_OFF 0x00000014 ///< Receive frame mode register offset.
#define SSC_TFMR_OFF 0x0000001C ///< Transmit frame mode register offset.
#define SSC_DATLEN_MASK 0x0000001F ///< Data length.
#define SSC_LOOP 5 ///< Receiver loop mode.
#define SSC_DATDEF 5 ///< Transmit default value.
#define SSC_MSBF 7 ///< Most significant bit first.
#define SSC_DATNB_MASK 0x00000F00 ///< Data number per frame.
#define SSC_DATNB_SHIFT 8 ///< Least significant bit of data number per frame.
#define SSC_FSLEN_MASK 0x000F0000 ///< Receive frame sync. length.
#define SSC_FSLEN_SHIFT 16 ///< Least significant bit of receive frame sync. length.
#define SSC_FSOS 0x00700000 ///< Receive frame sync. output selection.
#define SSC_FSOS_NONE 0x00000000 ///< No frame sync. Line set to input.
#define SSC_FSOS_NEGATIVE 0x00100000 ///< Negative pulse.
#define SSC_FSOS_POSITIVE 0x00200000 ///< Positive pulse.
#define SSC_FSOS_LOW 0x00300000 ///< Low during transfer.
#define SSC_FSOS_HIGH 0x00400000 ///< High during transfer.
#define SSC_FSOS_TOGGLE 0x00500000 ///< Toggling at each start.
#define SSC_FSDEN 23 ///< Frame sync. data enable.
#define SSC_FSEDGE 24 ///< Frame sync. edge detection.
/*\}*/
/**
* SSC Receive Holding Register
*/
/*\{*/
#define SSC_RHR_OFF 0x00000020 ///< Receive holding register offset.
/*\}*/
/**
* SSC Transmit Holding Register
*/
/*\{*/
#define SSC_THR_OFF 0x00000024 ///< Transmit holding register offset.
/*\}*/
/**
* SSC Receive Sync. Holding Register
*/
/*\{*/
#define SSC_RSHR_OFF 0x00000030 ///< Receive sync. holding register offset.
/*\}*/
/**
* SSC Transmit Sync. Holding Register
*/
/*\{*/
#define SSC_TSHR_OFF 0x00000034 ///< Transmit sync. holding register offset.
/*\}*/
/**
* SSC Receive Compare 0 Register
*/
/*\{*/
#define SSC_RC0R_OFF 0x00000038 ///< Receive compare 0 register offset.
/*\}*/
/**
* SSC Receive Compare 1 Register
*/
/*\{*/
#define SSC_RC1R_OFF 0x0000003C ///< Receive compare 1 register offset.
/*\}*/
/**
* SSC Status and Interrupt Register
*/
/*\{*/
#define SSC_SR_OFF 0x00000040 ///< Status register offset.
#define SSC_IER_OFF 0x00000044 ///< Interrupt enable register offset.
#define SSC_IDR_OFF 0x00000048 ///< Interrupt disable register offset.
#define SSC_IMR_OFF 0x0000004C ///< Interrupt mask register offset.
#define SSC_TXRDY 0 ///< Transmit ready.
#define SSC_TXEMPTY 1 ///< Transmit empty.
#define SSC_ENDTX 2 ///< End of transmission.
#define SSC_TXBUFE 3 ///< Transmit buffer empty.
#define SSC_RXRDY 4 ///< Receive ready.
#define SSC_OVRUN 5 ///< Receive overrun.
#define SSC_ENDRX 6 ///< End of receiption.
#define SSC_RXBUFF 7 ///< Receive buffer full.
#define SSC_CP0 8 ///< Compare 0.
#define SSC_CP1 9 ///< Compare 1.
#define SSC_TXSYN 10 ///< Transmit sync.
#define SSC_RXSYN 11 ///< Receive sync.
#define SSC_TXENA 16 ///< Transmit enable.
#define SSC_RXENA 17 ///< Receive enable.
#if defined(SSC_BASE)
#define SSC_CR (*((reg32_t *)(SSC_BASE + SSC_CR_OFF))) ///< Control register address.
#define SSC_CMR (*((reg32_t *)(SSC_BASE + SSC_CMR_OFF))) ///< Clock mode register address.
#define SSC_RCMR (*((reg32_t *)(SSC_BASE + SSC_RCMR_OFF))) ///< Receive clock mode register address.
#define SSC_TCMR (*((reg32_t *)(SSC_BASE + SSC_TCMR_OFF))) ///< Transmit clock mode register address.
#define SSC_RFMR (*((reg32_t *)(SSC_BASE + SSC_RFMR_OFF))) ///< Receive frame mode register address.
#define SSC_TFMR (*((reg32_t *)(SSC_BASE + SSC_TFMR_OFF))) ///< Transmit frame mode register address.
#define SSC_RHR (*((reg32_t *)(SSC_BASE + SSC_RHR_OFF))) ///< Receive holding register address.
#define SSC_THR (*((reg32_t *)(SSC_BASE + SSC_THR_OFF))) ///< Transmit holding register address.
#define SSC_RSHR (*((reg32_t *)(SSC_BASE + SSC_RSHR_OFF))) ///< Receive sync. holding register address.
#define SSC_TSHR (*((reg32_t *)(SSC_BASE + SSC_TSHR_OFF))) ///< Transmit sync. holding register address.
#define SSC_RC0R (*((reg32_t *)(SSC_BASE + SSC_RC0R_OFF))) ///< Receive compare 0 register address.
#define SSC_RC1R (*((reg32_t *)(SSC_BASE + SSC_RC1R_OFF))) ///< Receive compare 1 register address.
#define SSC_SR (*((reg32_t *)(SSC_BASE + SSC_SR_OFF))) ///< Status register address.
#define SSC_IER (*((reg32_t *)(SSC_BASE + SSC_IER_OFF))) ///< Interrupt enable register address.
#define SSC_IDR (*((reg32_t *)(SSC_BASE + SSC_IDR_OFF))) ///< Interrupt disable register address.
#define SSC_IMR (*((reg32_t *)(SSC_BASE + SSC_IMR_OFF))) ///< Interrupt mask register address.
#if defined(SSC_HAS_PDC)
#define SSC_RPR (*((reg32_t *)(SSC_BASE + PERIPH_RPR_OFF))) ///< PDC receive pointer register address.
#define SSC_RCR (*((reg32_t *)(SSC_BASE + PERIPH_RCR_OFF))) ///< PDC receive counter register address.
#define SSC_TPR (*((reg32_t *)(SSC_BASE + PERIPH_TPR_OFF))) ///< PDC transmit pointer register address.
#define SSC_TCR (*((reg32_t *)(SSC_BASE + PERIPH_TCR_OFF))) ///< PDC transmit counter register address.
#define SSC_RNPR (*((reg32_t *)(SSC_BASE + PERIPH_RNPR_OFF))) ///< PDC receive next pointer register address.
#define SSC_RNCR (*((reg32_t *)(SSC_BASE + PERIPH_RNCR_OFF))) ///< PDC receive next counter register address.
#define SSC_TNPR (*((reg32_t *)(SSC_BASE + PERIPH_TNPR_OFF))) ///< PDC transmit next pointer register address.
#define SSC_TNCR (*((reg32_t *)(SSC_BASE + PERIPH_TNCR_OFF))) ///< PDC transmit next counter register address.
#define SSC_PTCR (*((reg32_t *)(SSC_BASE + PERIPH_PTCR_OFF))) ///< PDC transfer control register address.
#define SSC_PTSR (*((reg32_t *)(SSC_BASE + PERIPH_PTSR_OFF))) ///< PDC transfer status register address.
#endif /* SSC_HAS_PDC */
#endif /* SSC_BASE */
#endif /* AT91_SSC_H */

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/**
* \file
* <!--
* This file is part of BeRTOS.
*
* Bertos is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* As a special exception, you may use this file as part of a free software
* library without restriction. Specifically, if other files instantiate
* templates or use macros or inline functions from this file, or you compile
* this file and link it with other files to produce an executable, this
* file does not by itself cause the resulting executable to be covered by
* the GNU General Public License. This exception does not however
* invalidate any other reasons why the executable file might be covered by
* the GNU General Public License.
*
* Copyright 2007 Develer S.r.l. (http://www.develer.com/)
*
* -->
*
*
* \author Daniele Basile <asterix@develer.com>
*
* AT91SAM7 Conunter timer definition.
* This file is based on NUT/OS implementation. See license below.
*/
/*
* Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
* SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* For additional information see http://www.ethernut.de/
*/
#ifndef AT91_TC_H
#define AT91_TC_H
/**
* Timer Counter Control Register
*/
#define TC_TC0_OFF 0x00000000 ///< Channel 0 control register offset.
#define TC_TC1_OFF 0x00000040 ///< Channel 1 control register offset.
#define TC_TC2_OFF 0x00000080 ///< Channel 2 control register offset.
#define TC0_CCR (*((reg32_t *)(TC_BASE + TC_TC0_OFF))) ///< Channel 0 control register address.
#define TC1_CCR (*((reg32_t *)(TC_BASE + TC_TC1_OFF))) ///< Channel 1 control register address.
#define TC2_CCR (*((reg32_t *)(TC_BASE + TC_TC2_OFF))) ///< Channel 2 control register address.
#define TC_CLKEN 0 ///< Clock enable command.
#define TC_CLKDIS 1 ///< Clock disable command.
#define TC_SWTRG 2 ///< Software trigger command.
/**
* Timer Counter Channel Mode Register
*/
#define TC_CMR_OFF 0x00000004 ///< Mode register offset.
#define TC0_CMR (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_CMR_OFF))) ///< Channel 0 mode register address.
#define TC1_CMR (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_CMR_OFF))) ///< Channel 1 mode register address.
#define TC2_CMR (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_CMR_OFF))) ///< Channel 2 mode register address.
#define TC_CLKS_MASK 0x00000007 ///< Clock selection mask.
#define TC_CLKS_MCK2 0x00000000 ///< Selects MCK / 2.
#define TC_CLKS_MCK8 0x00000001 ///< Selects MCK / 8.
#define TC_CLKS_MCK32 0x00000002 ///< Selects MCK / 32.
#define TC_CLKS_MCK128 0x00000003 ///< Selects MCK / 128.
#define TC_CLKS_MCK1024 0x00000004 ///< Selects MCK / 1024.
#define TC_CLKS_XC0 0x00000005 ///< Selects external clock 0.
#define TC_CLKS_XC1 0x00000006 ///< Selects external clock 1.
#define TC_CLKS_XC2 0x00000007 ///< Selects external clock 2.
#define TC_CLKI 3 ///< Increments on falling edge.
#define TC_BURST_MASK 0x00000030 ///< Burst signal selection mask.
#define TC_BURST_NONE 0x00000000 ///< Clock is not gated by an external signal.
#define TC_BUSRT_XC0 0x00000010 ///< ANDed with external clock 0.
#define TC_BURST_XC1 0x00000020 ///< ANDed with external clock 1.
#define TC_BURST_XC2 0x00000030 ///< ANDed with external clock 2.
#define TC_WAVE 15 ///< Selects waveform mode.
//To select capture mode you must set TC_WAVE bit to 0.
//#define TC_CAPT 15 ///< Selects capture mode.
/**
* Capture Mode
*/
#define TC_CPCTRG 14 ///< RC Compare Enable Trigger Enable.
#define TC_LDBSTOP 6 ///< Counter clock stopped on RB loading.
#define TC_LDBDIS 7 ///< Counter clock disabled on RB loading.
#define TC_ETRGEDG_MASK 0x00000300 ///< External trigger edge selection mask.
#define TC_ETRGEDG_RISING_EDGE 0x00000100 ///< Trigger on external rising edge.
#define TC_ETRGEDG_FALLING_EDGE 0x00000200 ///< Trigger on external falling edge.
#define TC_ETRGEDG_BOTH_EDGE 0x00000300 ///< Trigger on both external edges.
#define TC_ABETRG_MASK 0x00000400 ///< TIOA or TIOB external trigger selection mask.
#define TC_ABETRG_TIOA 10 ///< TIOA used as an external trigger.
//To use external trigger TIOB you must set TC_ABETRG_TIOA bit to 0.
//#define TC_ABETRG_TIOB 10 ///< TIOB used as an external trigger.
#define TC_LDRA_MASK 0x00030000 ///< RA loading selection mask.
#define TC_LDRA_RISING_EDGE 0x00010000 ///< Load RA on rising edge of TIOA.
#define TC_LDRA_FALLING_EDGE 0x00020000 ///< Load RA on falling edge of TIOA.
#define TC_LDRA_BOTH_EDGE 0x00030000 ///< Load RA on any edge of TIOA.
#define TC_LDRB_MASK 0x000C0000 ///< RB loading selection mask.
#define TC_LDRB_RISING_EDGE 0x00040000 ///< Load RB on rising edge of TIOA.
#define TC_LDRB_FALLING_EDGE 0x00080000 ///< Load RB on falling edge of TIOA.
#define TC_LDRB_BOTH_EDGE 0x000C0000 ///< Load RB on any edge of TIOA.
/**
* Waveform Mode
*/
#define TC_CPCSTOP 6 ///< Counter clock stopped on RC compare.
#define TC_CPCDIS 7 ///< Counter clock disabled on RC compare.
#define TC_EEVTEDG_MASK 0x00000300 ///< External event edge selection mask.
#define TC_EEVTEDG_RISING_EDGE 0x00000100 ///< External event on rising edge..
#define TC_EEVTEDG_FALLING_EDGE 0x00000200 ///< External event on falling edge..
#define TC_EEVTEDG_BOTH_EDGE 0x00000300 ///< External event on any edge..
#define TC_EEVT_MASK 0x00000C00 ///< External event selection mask.
#define TC_EEVT_TIOB 0x00000000 ///< TIOB selected as external event.
#define TC_EEVT_XC0 0x00000400 ///< XC0 selected as external event.
#define TC_EEVT_XC1 0x00000800 ///< XC1 selected as external event.
#define TC_EEVT_XC2 0x00000C00 ///< XC2 selected as external event.
#define TC_ENETRG 12 ///< External event trigger enable.
#define TC_WAVSEL_MASK 0x00006000 ///< Waveform selection mask.
#define TC_WAVSEL_UP 0x00000000 ///< UP mode whitout automatic trigger on RC compare.
#define TC_WAVSEL_UP_RC_TRG 0x00004000 ///< UP mode whit automatic trigger on RC compare.
#define TC_WAVSEL_UPDOWN 0x00002000 ///< UPDOWN mode whitout automatic trigger on RC compare.
#define TC_WAVSEL_UPDOWN_RC_TRG 0x00003000 ///< UPDOWN mode whit automatic trigger on RC compare.
#define TC_ACPA_MASK 0x00030000 ///< Masks RA compare effect on TIOA.
#define TC_ACPA_SET_OUTPUT 0x00010000 ///< RA compare sets TIOA.
#define TC_ACPA_CLEAR_OUTPUT 0x00020000 ///< RA compare clears TIOA.
#define TC_ACPA_TOGGLE_OUTPUT 0x00030000 ///< RA compare toggles TIOA.
#define TC_ACPC_MASK 0x000C0000 ///< Masks RC compare effect on TIOA.
#define TC_ACPC_SET_OUTPUT 0x00040000 ///< RC compare sets TIOA.
#define TC_ACPC_CLEAR_OUTPUT 0x00080000 ///< RC compare clears TIOA.
#define TC_ACPC_TOGGLE_OUTPUT 0x000C0000 ///< RC compare toggles TIOA.
#define TC_AEEVT_MASK 0x00300000 ///< Masks external event effect on TIOA.
#define TC_AEEVT_SET_OUTPUT 0x00100000 ///< External event sets TIOA.
#define TC_AEEVT_CLEAR_OUTPUT 0x00200000 ///< External event clears TIOA.
#define TC_AEEVT_TOGGLE_OUTPUT 0x00300000 ///< External event toggles TIOA.
#define TC_ASWTRG_MASK 0x00C00000 ///< Masks software trigger effect on TIOA.
#define TC_ASWTRG_SET_OUTPUT 0x00400000 ///< Software trigger sets TIOA.
#define TC_ASWTRG_CLEAR_OUTPUT 0x00800000 ///< Software trigger clears TIOA.
#define TC_ASWTRG_TOGGLE_OUTPUT 0x00C00000 ///< Software trigger toggles TIOA.
#define TC_BCPB_MASK 0x03000000 ///< Masks RB compare effect on TIOB.
#define TC_BCPB_SET_OUTPUT 0x01000000 ///< RB compare sets TIOB.
#define TC_BCPB_CLEAR_OUTPUT 0x02000000 ///< RB compare clears TIOB.
#define TC_BCPB_TOGGLE_OUTPUT 0x03000000 ///< RB compare toggles TIOB.
#define TC_BCPC_MASK 0x0C000000 ///< Masks RC compare effect on TIOB.
#define TC_BCPC_SET_OUTPUT 0x04000000 ///< RC compare sets TIOB.
#define TC_BCPC_CLEAR_OUTPUT 0x08000000 ///< RC compare clears TIOB.
#define TC_BCPC_TOGGLE_OUTPUT 0x0C000000 ///< RC compare toggles TIOB.
#define TC_BEEVT_MASK 0x30000000 ///< Masks external event effect on TIOB.
#define TC_BEEVT_SET_OUTPUT 0x10000000 ///< External event sets TIOB.
#define TC_BEEVT_CLEAR_OUTPUT 0x20000000 ///< External event clears TIOB.
#define TC_BEEVT_TOGGLE_OUTPUT 0x30000000 ///< External event toggles TIOB.
#define TC_BSWTRG_MASK 0xC0000000 ///< Masks software trigger effect on TIOB.
#define TC_BSWTRG_SET_OUTPUT 0x40000000 ///< Software trigger sets TIOB.
#define TC_BSWTRG_CLEAR_OUTPUT 0x80000000 ///< Software trigger clears TIOB.
#define TC_BSWTRG_TOGGLE_OUTPUT 0xC0000000 ///< Software trigger toggles TIOB.
/**
* Counter Value Register
*/
#define TC_CV_OFF 0x00000010 ///< Counter register value offset.
#define TC0_CV (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_CV_OFF))) ///< Counter 0 value.
#define TC1_CV (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_CV_OFF))) ///< Counter 1 value.
#define TC2_CV (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_CV_OFF))) ///< Counter 2 value.
/**
* Timer Counter Register A
*/
#define TC_RA_OFF 0x00000014 ///< Register A offset.
#define TC0_RA (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_RA_OFF))) ///< Channel 0 register A.
#define TC1_RA (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_RA_OFF))) ///< Channel 1 register A.
#define TC2_RA (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_RA_OFF))) ///< Channel 2 register A.
/**
* Timer Counter Register B
*/
#define TC_RB_OFF 0x00000018 ///< Register B offset.
#define TC0_RB (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_RB_OFF))) ///< Channel 0 register B.
#define TC1_RB (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_RB_OFF))) ///< Channel 1 register B.
#define TC2_RB (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_RB_OFF))) ///< Channel 2 register B.
/**
* Timer Counter Register C
*/
#define TC_RC_OFF 0x0000001C ///< Register C offset.
#define TC0_RC (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_RC_OFF))) ///< Channel 0 register C.
#define TC1_RC (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_RC_OFF))) ///< Channel 1 register C.
#define TC2_RC (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_RC_OFF))) ///< Channel 2 register C.
/**
* Timer Counter Status and Interrupt Registers
*/
#define TC_SR_OFF 0x00000020 ///< Status Register offset.
#define TC0_SR (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_SR_OFF))) ///< Status register address.
#define TC1_SR (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_SR_OFF))) ///< Status register address.
#define TC2_SR (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_SR_OFF))) ///< Status register address.
#define TC_IER_OFF 0x00000024 ///< Interrupt Enable Register offset.
#define TC0_IER (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_IER_OFF))) ///< Channel 0 interrupt enable register address.
#define TC1_IER (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_IER_OFF))) ///< Channel 1 interrupt enable register address.
#define TC2_IER (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_IER_OFF))) ///< Channel 2 interrupt enable register address.
#define TC_IDR_OFF 0x00000028 ///< Interrupt Disable Register offset.
#define TC0_IDR (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_IDR_OFF))) ///< Channel 0 interrupt disable register address.
#define TC1_IDR (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_IDR_OFF))) ///< Channel 1 interrupt disable register address.
#define TC2_IDR (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_IDR_OFF))) ///< Channel 2 interrupt disable register address.
#define TC_IMR_OFF 0x0000002C ///< Interrupt Mask Register offset.
#define TC0_IMR (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_IMR_OFF))) ///< Channel 0 interrupt mask register address.
#define TC1_IMR (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_IMR_OFF))) ///< Channel 1 interrupt mask register address.
#define TC2_IMR (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_IMR_OFF))) ///< Channel 2 interrupt mask register address.
#define TC_COVFS 0 ///< Counter overflow flag.
#define TC_LOVRS 1 ///< Load overrun flag.
#define TC_CPAS 2 ///< RA compare flag.
#define TC_CPBS 3 ///< RB compare flag.
#define TC_CPCS 4 ///< RC compare flag.
#define TC_LDRAS 5 ///< RA loading flag.
#define TC_LDRBS 6 ///< RB loading flag.
#define TC_ETRGS 7 ///< External trigger flag.
#define TC_CLKSTA 16 ///< Clock enable flag.
#define TC_MTIOA 17 ///< TIOA flag.
#define TC_MTIOB 18 ///< TIOB flag.
/**
* Timer Counter Block Control Register
*/
#define TC_BCR_OFF 0x000000C0 ///< Block control register offset.
#define TC_BCR (*((reg32_t *)(TC_BASE + TC_BCR_OFF))) ///< Block control register address.
#define TC_SYNC 0 ///< Synchronisation trigger
/**
* Timer Counter Block Mode Register
*/
#define TC_BMR_OFF 0x000000C4 ///< Block mode register offset.
#define TC_BMR (*((reg32_t *)(TC_BASE + TC_BMR_OFF))) ///< Block mode register address.
#define TC_TC0XC0S 0x00000003 ///< External clock signal 0 selection mask.
#define TC_TCLK0XC0 0x00000000 ///< Selects TCLK0.
#define TC_NONEXC0 0x00000001 ///< None selected.
#define TC_TIOA1XC0 0x00000002 ///< Selects TIOA1.
#define TC_TIOA2XC0 0x00000003 ///< Selects TIOA2.
#define TC_TC1XC1S 0x0000000C ///< External clock signal 1 selection mask.
#define TC_TCLK1XC1 0x00000000 ///< Selects TCLK1.
#define TC_NONEXC1 0x00000004 ///< None selected.
#define TC_TIOA0XC1 0x00000008 ///< Selects TIOA0.
#define TC_TIOA2XC1 0x0000000C ///< Selects TIOA2.
#define TC_TC2XC2S 0x00000030 ///< External clock signal 2 selection mask.
#define TC_TCLK2XC2 0x00000000 ///< Selects TCLK2.
#define TC_NONEXC2 0x00000010 ///< None selected.
#define TC_TIOA0XC2 0x00000020 ///< Selects TIOA0.
#define TC_TIOA1XC2 0x00000030 ///< Selects TIOA1.
#endif /* AT91_TC_H */

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/**
* \file
* <!--
* This file is part of BeRTOS.
*
* Bertos is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* As a special exception, you may use this file as part of a free software
* library without restriction. Specifically, if other files instantiate
* templates or use macros or inline functions from this file, or you compile
* this file and link it with other files to produce an executable, this
* file does not by itself cause the resulting executable to be covered by
* the GNU General Public License. This exception does not however
* invalidate any other reasons why the executable file might be covered by
* the GNU General Public License.
*
* Copyright 2008 Develer S.r.l. (http://www.develer.com/)
*
* -->
*
*
* \author Francesco Sacchi <batt@develer.com>
*
* AT91SAM7 Two wire interface.
* This file is based on NUT/OS implementation. See license below.
*/
/*
* Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
* SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (*((reg32_t *)(INCLUDING NEGLIGENCE OR OTHERWISE))) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* For additional information see http://www.ethernut.de/
*/
#ifndef AT91_TWI_H
#define AT91_TWI_H
/**
* TWI Control Register.
* \{
*/
#define TWI_CR_OFF 0x00000000 ///< Control register offset.
#define TWI_CR (*((reg32_t *)(TWI_BASE + TWI_CR_OFF))) ///< Control register address.
#define TWI_START 0 ///< Send start condition.
#define TWI_STOP 1 ///< Send stop condition.
#define TWI_MSEN 2 ///< Enable master mode.
#define TWI_MSDIS 3 ///< Disable master mode.
/*
#define TWI_SVEN 4 ///< Enable slave mode.
#define TWI_SVDIS 5 ///< Disable slave mode.
*/
#define TWI_SWRST 7 ///< Software reset.
/*\}*/
/**
* TWI Master Mode Register.
* \{
*/
#define TWI_MMR_OFF 0x00000004 ///< Master mode register offset.
#define TWI_MMR (*((reg32_t *)(TWI_BASE + TWI_MMR_OFF))) ///< Master mode register address.
#define TWI_IADRSZ_SHIFT 8 ///< Internal device address size shift.
#define TWI_IADRSZ 0x00000300 ///< Internal device address size mask.
#define TWI_IADRSZ_NONE 0x00000000 ///< No internal device address.
#define TWI_IADRSZ_1BYTE 0x00000100 ///< One byte internal device address.
#define TWI_IADRSZ_2BYTE 0x00000200 ///< Two byte internal device address.
#define TWI_IADRSZ_3BYTE 0x00000300 ///< Three byte internal device address.
#define TWI_MREAD 12 ///< Master read direction.
#define TWI_DADR 0x007F0000 ///< Device address mask.
#define TWI_DADR_SHIFT 16 ///< Device address LSB.
/*\}*/
/**
* TWI Internal Address Register.
* \{
*/
#define TWI_IADR_OFF 0x0000000C ///< Internal address register offset.
#define TWI_IADR (*((reg32_t *)(TWI_BASE + TWI_IADR_OFF))) ///< Internal address register address.
#define TWI_IADR_MASK 0x00FFFFFF ///< Internal address mask.
#define TWI_IADR_SHIFT 0 ///< Internal address LSB.
/*\}*/
/**
* TWI Clock Waveform Generator Register.
* \{
*/
#define TWI_CWGR_OFF 0x00000010 ///< Clock waveform generator register offset.
#define TWI_CWGR (*((reg32_t *)(TWI_BASE + TWI_CWGR_OFF))) ///< Clock waveform generator register address.
#define TWI_CLDIV 0x000000FF ///< Clock low divider mask.
#define TWI_CLDIV_SHIFT 0 ///< Clock low divider LSB.
#define TWI_CHDIV 0x0000FF00 ///< Clock high divider mask.
#define TWI_CHDIV_SHIFT 8 ///< Clock high divider LSB.
#define TWI_CKDIV 0x00070000 ///< Clock divider mask.
#define TWI_CKDIV_SHIFT 16 ///< Clock divider LSB.
/*\}*/
/**
* TWI Status and Interrupt Registers.
* \{
*/
#define TWI_SR_OFF 0x00000020 ///< Status register offset.
#define TWI_SR (*((reg32_t *)(TWI_BASE + TWI_SR_OFF))) ///< Status register address.
#define TWI_IER_OFF 0x00000024 ///< Interrupt enable register offset.
#define TWI_IER (*((reg32_t *)(TWI_BASE + TWI_IER_OFF))) ///< Interrupt enable register address.
#define TWI_IDR_OFF 0x00000028 ///< Interrupt disable register offset.
#define TWI_IDR (*((reg32_t *)(TWI_BASE + TWI_IDR_OFF))) ///< Interrupt disable register address.
#define TWI_IMR_OFF 0x0000002C ///< Interrupt mask register offset.
#define TWI_IMR (*((reg32_t *)(TWI_BASE + TWI_IMR_OFF))) ///< Interrupt mask register address.
#define TWI_TXCOMP 0 ///< Transmission completed.
#define TWI_RXRDY 1 ///< Receive holding register ready.
#define TWI_TXRDY 2 ///< Transmit holding register ready.
/*
#define TWI_SVREAD 0x00000008 ///< Slave read.
#define TWI_SVACC 0x00000010 ///< Slave access.
#define TWI_GACC 0x00000020 ///< General call access.
*/
#if CPU_ARM_SAM7X
#define TWI_OVRE 6 ///< Overrun error.
#define TWI_UNRE 7 ///< Underrun error.
#endif
#define TWI_NACK 8 ///< Not acknowledged.
/*
#define TWI_ARBLST 0x00000200 ///< Arbitration lost.
#define TWI_SCLWS 0x00000400 ///< Clock wait state.
#define TWI_EOSACC 0x00000800 ///< End of slave access.
*/
/*\}*/
/**
* TWI Receive Holding Register.
* \{
*/
#define TWI_RHR_OFF 0x00000030 ///< Receive holding register offset.
#define TWI_RHR (*((reg32_t *)(TWI_BASE + TWI_RHR_OFF))) ///< Receive holding register address.
/*\}*/
/**
* TWI Transmit Holding Register.
* \{
*/
#define TWI_THR_OFF 0x00000034 ///< Transmit holding register offset.
#define TWI_THR (*((reg32_t *)(TWI_BASE + TWI_THR_OFF))) ///< Transmit holding register address.
/*\}*/
#endif /* AT91_TWI_H */

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/**
* \file
* <!--
* This file is part of BeRTOS.
*
* Bertos is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* As a special exception, you may use this file as part of a free software
* library without restriction. Specifically, if other files instantiate
* templates or use macros or inline functions from this file, or you compile
* this file and link it with other files to produce an executable, this
* file does not by itself cause the resulting executable to be covered by
* the GNU General Public License. This exception does not however
* invalidate any other reasons why the executable file might be covered by
* the GNU General Public License.
*
* Copyright 2007 Develer S.r.l. (http://www.develer.com/)
*
* -->
*
*
* \author Daniele Basile <asterix@develer.com>
*
* AT91 UART User interface.
* This file is based on NUT/OS implementation. See license below.
*/
/*
* Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
* SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* For additional information see http://www.ethernut.de/
*/
#ifndef AT91_US_H
#define AT91_US_H
/**
* USART Control Register
*/
/*\{*/
#define US_CR_OFF 0x00000000 ///< USART control register offset.
#define US0_CR (*((reg32_t *)(USART0_BASE + US_CR_OFF))) ///< Channel 0 control register address.
#define US1_CR (*((reg32_t *)(USART1_BASE + US_CR_OFF))) ///< Channel 1 control register address.
#define US_RSTRX 2 ///< Reset receiver.
#define US_RSTTX 3 ///< Reset transmitter.
#define US_RXEN 4 ///< Receiver enable.
#define US_RXDIS 5 ///< Receiver disable.
#define US_TXEN 6 ///< Transmitter enable.
#define US_TXDIS 7 ///< Transmitter disable.
#define US_RSTSTA 8 ///< Reset status bits.
#define US_STTBRK 9 ///< Start break.
#define US_STPBRK 10 ///< Stop break.
#define US_STTTO 11 ///< Start timeout.
#define US_SENDA 12 ///< Send next byte with address bit set.
#define US_RSTIT 13 ///< Reset interations.
#define US_RSTNAK 14 ///< Reset non acknowledge.
#define US_RETTO 15 ///< Rearm time out.
#define US_DTREN 16 ///< Data terminal ready enable.
#define US_DTRDIS 17 ///< Data terminal ready disable.
#define US_RTSEN 18 ///< Request to send enable.
#define US_RTSDIS 19 ///< Request to send disable.
/*\}*/
/**
* Mode Register
*/
/*\{*/
#define US_MR_OFF 0x00000004 ///< USART mode register offset.
#define US0_MR (*((reg32_t *)(USART0_BASE + US_MR_OFF))) ///< Channel 0 mode register address.
#define US1_MR (*((reg32_t *)(USART1_BASE + US_MR_OFF))) ///< Channel 1 mode register address.
#define US_USART_MODE_MASK 0x0000000F ///< USART mode mask.
#define US_USART_MODE_NORMA 0x00000000 ///< Normal.
#define US_USART_MODE_RS485 0x00000001 ///< RS485.
#define US_USART_MODE_HW_HDSH 0x00000002 ///< Hardware handshaking.
#define US_USART_MODE_MODEM 0x00000003 ///< Modem.
#define US_USART_MODE_ISO7816T0 0x00000004 ///< ISO7816 protocol: T=0.
#define US_USART_MODE_ISO7816T1 0x00000006 ///< ISO7816 protocol: T=1.
#define US_USART_MODE_IRDA 0x00000008 ///< IrDA.
#define US_CLKS_MASK 0x00000030 ///< Clock selection mask.
#define US_CLKS_MCK 0x00000000 ///< Master clock.
#define US_CLKS_MCK8 0x00000010 ///< Master clock divided by 8.
#define US_CLKS_SCK 0x00000020 ///< External clock.
#define US_CLKS_SLCK 0x00000030 ///< Slow clock.
#define US_CHRL_MASK 0x000000C0 ///< Masks data length.
#define US_CHRL_5 0x00000000 ///< 5 data bits.
#define US_CHRL_6 0x00000040 ///< 6 data bits.
#define US_CHRL_7 0x00000080 ///< 7 data bits.
#define US_CHRL_8 0x000000C0 ///< 8 data bits.
#define US_SYNC 8 ///< Synchronous mode enable.
#define US_PAR_MASK 0x00000E00 ///< Parity mode mask.
#define US_PAR_EVEN 0x00000000 ///< Even parity.
#define US_PAR_ODD 0x00000200 ///< Odd parity.
#define US_PAR_SPACE 0x00000400 ///< Space parity.
#define US_PAR_MARK 0x00000600 ///< Marked parity.
#define US_PAR_NO 0x00000800 ///< No parity.
#define US_PAR_MULTIDROP 0x00000C00 ///< Multi-drop mode.
#define US_NBSTOP_MASK 0x00003000 ///< Masks stop bit length.
#define US_NBSTOP_1 0x00000000 ///< 1 stop bit.
#define US_NBSTOP_1_5 0x00001000 ///< 1.5 stop bits.
#define US_NBSTOP_2 0x00002000 ///< 2 stop bits.
#define US_CHMODE_MASK 0x0000C000 ///< Channel mode mask.
#define US_CHMODE_NORMAL 0x00000000 ///< Normal mode.
#define US_CHMODE_AUTOMATIC_ECHO 0x00004000 ///< Automatic echo.
#define US_CHMODE_LOCAL_LOOPBACK 0x00008000 ///< Local loopback.
#define US_CHMODE_REMOTE_LOOPBACK 0x0000C000 ///< Remote loopback.
#define US_MSBF 16 ///< Bit order.
#define US_MODE9 17 ///< 9 bit mode.
#define US_CLKO 18 ///< Clock output select.
#define US_OVER 19 ///< Oversampling mode.
#define US_INACK 20 ///< Inhibit non acknowledge.
#define US_DSNACK 21 ///< Disable successive nack.
#define US_MAX_INTERATION_MASK 0x07000000 ///< Max numer of interation in mode ISO7816 T=0.
#define US_FILTER 28 ///< Infrared receive line filter.
/*\}*/
/**
* Status and Interrupt Register
*/
/*\{*/
#define US_IER_OFF 0x00000008 ///< USART interrupt enable register offset.
#define US0_IER (*((reg32_t *)(USART0_BASE + US_IER_OFF))) ///< Channel 0 interrupt enable register address.
#define US1_IER (*((reg32_t *)(USART1_BASE + US_IER_OFF))) ///< Channel 1 interrupt enable register address.
#define US_IDR_OFF 0x0000000C ///< USART interrupt disable register offset.
#define US0_IDR (*((reg32_t *)(USART0_BASE + US_IDR_OFF))) ///< Channel 0 interrupt disable register address.
#define US1_IDR (*((reg32_t *)(USART1_BASE + US_IDR_OFF))) ///< Channel 1 interrupt disable register address.
#define US_IMR_OFF 0x00000010 ///< USART interrupt mask register offset.
#define US0_IMR (*((reg32_t *)(USART0_BASE + US_IMR_OFF))) ///< Channel 0 interrupt mask register address.
#define US1_IMR (*((reg32_t *)(USART1_BASE + US_IMR_OFF))) ///< Channel 1 interrupt mask register address.
#define US_CSR_OFF 0x00000014 ///< USART status register offset.
#define US0_CSR (*((reg32_t *)(USART0_BASE + US_CSR_OFF))) ///< Channel 0 status register address.
#define US1_CSR (*((reg32_t *)(USART1_BASE + US_CSR_OFF))) ///< Channel 1 status register address.
#define US_CSR_RI 20 ///< Image of RI input.
#define US_CSR_DSR 21 ///< Image of DSR input.
#define US_CSR_DCD 22 ///< Image of DCD input.
#define US_CSR_CTS 23 ///< Image of CTS input.
#define US_RXRDY 0 ///< Receiver ready.
#define US_TXRDY 1 ///< Transmitter ready.
#define US_RXBRK 2 ///< Receiver break.
#define US_ENDRX 3 ///< End of receiver PDC transfer.
#define US_ENDTX 4 ///< End of transmitter PDC transfer.
#define US_OVRE 5 ///< Overrun error.
#define US_FRAME 6 ///< Framing error.
#define US_PARE 7 ///< Parity error.
#define US_TIMEOUT 8 ///< Receiver timeout.
#define US_TXEMPTY 9 ///< Transmitter empty.
#define US_ITERATION 10 ///< Iteration interrupt enable.
#define US_TXBUFE 11 ///< Buffer empty interrupt enable.
#define US_RXBUFF 12 ///< Buffer full interrupt enable.
#define US_NACK 13 ///< Non acknowledge interrupt enable.
#define US_RIIC 16 ///< Ring indicator input change enable.
#define US_DSRIC 17 ///< Data set ready input change enable.
#define US_DCDIC 18 ///< Data carrier detect input change interrupt enable.
#define US_CTSIC 19 ///< Clear to send input change interrupt enable.
/**
* Receiver Holding Register
*/
/*\{*/
#define US_RHR_OFF 0x00000018 ///< USART receiver holding register offset.
#define US0_RHR (*((reg32_t *)(USART0_BASE + US_RHR_OFF))) ///< Channel 0 receiver holding register address.
#define US1_RHR (*((reg32_t *)(USART1_BASE + US_RHR_OFF))) ///< Channel 1 receiver holding register address.
#define US_RHR_RXCHR_MASK 0x000001FF ///< Last char received if US_RXRDY is set.
#define US_RHR_RXSYNH 15 ///< Received sync.
/*\}*/
/**
* Transmitter Holding Register
*/
/*\{*/
#define US_THR_OFF 0x0000001C ///< USART transmitter holding register offset.
#define US0_THR (*((reg32_t *)(USART0_BASE + US_THR_OFF))) ///< Channel 0 transmitter holding register address.
#define US1_THR (*((reg32_t *)(USART1_BASE + US_THR_OFF))) ///< Channel 1 transmitter holding register address.
#define US_THR_TXCHR_MASK 0x000001FF ///< Next char to be trasmitted.
#define US_THR_TXSYNH 15 ///< Sync field to be trasmitted.
/*\}*/
/**
* Baud Rate Generator Register
*/
/*\{*/
#define US_BRGR_OFF 0x00000020 ///< USART baud rate register offset.
#define US0_BRGR (*((reg32_t *)(USART0_BASE + US_BRGR_OFF))) ///< Channel 0 baud rate register address.
#define US1_BRGR (*((reg32_t *)(USART1_BASE + US_BRGR_OFF))) ///< Channel 1 baud rate register address.
/*\}*/
/**
* Receiver Timeout Register
*/
/*\{*/
#define US_RTOR_OFF 0x00000024 ///< USART receiver timeout register offset.
#define US0_RTOR (*((reg32_t *)(USART0_BASE + US_RTOR_OFF))) ///< Channel 0 receiver timeout register address.
#define US1_RTOR (*((reg32_t *)(USART1_BASE + US_RTOR_OFF))) ///< Channel 1 receiver timeout register address.
/*\}*/
/**
* Transmitter Time Guard Register
*/
/*\{*/
#define US_TTGR_OFF 0x00000028 ///< USART transmitter time guard register offset.
#define US0_TTGR (*((reg32_t *)(USART0_BASE + US_TTGR_OFF))) ///< Channel 0 transmitter time guard register address.
#define US1_TTGR (*((reg32_t *)(USART1_BASE + US_TTGR_OFF))) ///< Channel 1 transmitter time guard register address.
/*\}*/
/**
* FI DI Ratio Register
*/
/*\{*/
#define US_FIDI_OFF 0x00000040 ///< USART FI DI ratio register offset.
#define US0_FIDI (*((reg32_t *)(USART0_BASE + US_FIDI_OFF))) ///< Channel 0 FI DI ratio register address.
#define US1_FIDI (*((reg32_t *)(USART1_BASE + US_FIDI_OFF))) ///< Channel 1 FI DI ratio register address.
/*\}*/
/**
* Error Counter Register
*/
/*\{*/
#define US_NER_OFF 0x00000044 ///< USART error counter register offset.
#define US0_NER (*((reg32_t *)(USART0_BASE + US_NER_OFF))) ///< Channel 0 error counter register address.
#define US1_NER (*((reg32_t *)(USART1_BASE + US_NER_OFF))) ///< Channel 1 error counter register address.
/*\}*/
/**
* IrDA Filter Register
*/
/*\{*/
#define US_IF_OFF 0x0000004C ///< USART IrDA filter register offset.
#define US0_IF (*((reg32_t *)(USART0_BASE + US_IF_OFF))) ///< Channel 0 IrDA filter register address.
#define US1_IF (*((reg32_t *)(USART1_BASE + US_IF_OFF))) ///< Channel 1 IrDA filter register address.
/*\}*/
#if USART_HAS_PDC
/**
* Receive Pointer Register
*/
/*\{*/
#define US0_RPR (*((reg32_t *)(USART0_BASE + PERIPH_RPR_OFF))) ///< Channel 0 receive pointer register address.
#define US1_RPR (*((reg32_t *)(USART1_BASE + PERIPH_RPR_OFF))) ///< Channel 1 receive pointer register address.
/*\}*/
/**
* Receive Counter Register
*/
/*\{*/
#define US0_RCR (*((reg32_t *)(USART0_BASE + PERIPH_RCR_OFF))) ///< Channel 0 receive counter register address.
#define US1_RCR (*((reg32_t *)(USART1_BASE + PERIPH_RCR_OFF))) ///< Channel 1 receive counter register address.
/*\}*/
/**
* Transmit Pointer Register
*/
/*\{*/
#define US0_TPR (*((reg32_t *)(USART0_BASE + PERIPH_TPR_OFF))) ///< Channel 0 transmit pointer register address.
#define US1_TPR (*((reg32_t *)(USART1_BASE + PERIPH_TPR_OFF))) ///< Channel 1 transmit pointer register address.
/*\}*/
/**
* Transmit Counter Register
*/
/*\{*/
#define US0_TCR (*((reg32_t *)(USART0_BASE + PERIPH_TCR_OFF))) ///< Channel 0 transmit counter register address.
#define US1_TCR (*((reg32_t *)(USART1_BASE + PERIPH_TCR_OFF))) ///< Channel 1 transmit counter register address.
/*\}*/
#if defined(PERIPH_RNPR_OFF) && defined(PERIPH_RNCR_OFF)
#define US0_RNPR (*((reg32_t *)(USART0_BASE + PERIPH_RNPR_OFF))) ///< PDC channel 0 receive next pointer register.
#define US1_RNPR (*((reg32_t *)(USART1_BASE + PERIPH_RNPR_OFF))) ///< PDC channel 1 receive next pointer register.
#define US0_RNCR (*((reg32_t *)(USART0_BASE + PERIPH_RNCR_OFF))) ///< PDC channel 0 receive next counter register.
#define US1_RNCR (*((reg32_t *)(USART1_BASE + PERIPH_RNCR_OFF))) ///< PDC channel 1 receive next counter register.
#endif
#if defined(PERIPH_TNPR_OFF) && defined(PERIPH_TNCR_OFF)
#define US0_TNPR (*((reg32_t *)(USART0_BASE + PERIPH_TNPR_OFF))) ///< PDC channel 0 transmit next pointer register.
#define US1_TNPR (*((reg32_t *)(USART1_BASE + PERIPH_TNPR_OFF))) ///< PDC channel 1 transmit next pointer register.
#define US0_TNCR (*((reg32_t *)(USART0_BASE + PERIPH_TNCR_OFF))) ///< PDC channel 0 transmit next counter register.
#define US1_TNCR (*((reg32_t *)(USART1_BASE + PERIPH_TNCR_OFF))) ///< PDC channel 1 transmit next counter register.
#endif
#if defined(PERIPH_PTCR_OFF)
#define US0_PTCR (*((reg32_t *)(USART0_BASE + PERIPH_PTCR_OFF))) ///< PDC channel 0 transfer control register.
#define US1_PTCR (*((reg32_t *)(USART1_BASE + PERIPH_PTCR_OFF))) ///< PDC channel 1 transfer control register.
#endif
#if defined(PERIPH_PTSR_OFF)
#define US0_PTSR (*((reg32_t *)(USART0_BASE + PERIPH_PTSR_OFF))) ///< PDC channel 0 transfer status register.
#define US1_PTSR (*((reg32_t *)(USART1_BASE + PERIPH_PTSR_OFF))) ///< PDC channel 1 transfer status register.
#endif
#endif /* USART_HAS_PDC */
#endif /* AT91_US_H */

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/**
* \file
* <!--
* This file is part of BeRTOS.
*
* Bertos is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* As a special exception, you may use this file as part of a free software
* library without restriction. Specifically, if other files instantiate
* templates or use macros or inline functions from this file, or you compile
* this file and link it with other files to produce an executable, this
* file does not by itself cause the resulting executable to be covered by
* the GNU General Public License. This exception does not however
* invalidate any other reasons why the executable file might be covered by
* the GNU General Public License.
*
* Copyright 2007 Develer S.r.l. (http://www.develer.com/)
*
* -->
*
*
* \author Francesco Sacchi <batt@develer.com>
*
* AT91 Watchdog.
* This file is based on NUT/OS implementation. See license below.
*/
/*
* Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
* SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* For additional information see http://www.ethernut.de/
*/
#ifndef AT91_WDT_H
#define AT91_WDT_H
/** Watch Dog Control Register */
/*\{*/
#define WDT_CR_OFF 0x00000000 ///< Watchdog control register offset.
#define WDT_CR (*((reg32_t *)(WDT_BASE + WDT_CR_OFF))) ///< Watchdog control register address.
#define WDT_WDRSTT 0 ///< Watchdog restart.
#define WDT_KEY 0xA5000000 ///< Watchdog password.
/*\}*/
/** Watch Dog Mode Register */
/*\{*/
#define WDT_MR_OFF 0x00000004 ///< Mode register offset.
#define WDT_MR (*((reg32_t *)(WDT_BASE + WDT_MR_OFF))) ///< Mode register address.
#define WDT_WDV_MASK 0x00000FFF ///< Counter value mask.
#define WDT_WDV_SHIFT 0 ///< Counter value LSB.
#define WDT_WDFIEN 12 ///< Fault interrupt enable.
#define WDT_WDRSTEN 13 ///< Reset enable.
#define WDT_WDRPROC 14 ///< Eset processor enable.
#define WDT_WDDIS 15 ///< Watchdog disable.
#define WDT_WDD_MASK 0x0FFF0000 ///< Delta value mask.
#define WDT_WDD_SHIFT 16 ///< Delta value LSB.
#define WDT_WDDBGHLT 28 ///< Watchdog debug halt.
#define WDT_WDIDLEHLT 29 ///< Watchdog idle halt.
/*\}*/
/** Watch Dog Status Register */
/*\{*/
#define WDT_SR_OFF 0x00000008 ///< Status register offset.
#define WDT_SR (*((reg32_t *)(WDT_BASE + WDT_SR_OFF))) ///< Status register address.
#define WDT_WDUNF 0 ///< Watchdog underflow.
#define WDT_WDERR 1 ///< Watchdog error.
/*\}*/
#endif /* AT91_WDT_H */

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/**
* \file
* <!--
* This file is part of BeRTOS.
*
* Bertos is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
* As a special exception, you may use this file as part of a free software
* library without restriction. Specifically, if other files instantiate
* templates or use macros or inline functions from this file, or you compile
* this file and link it with other files to produce an executable, this
* file does not by itself cause the resulting executable to be covered by
* the GNU General Public License. This exception does not however
* invalidate any other reasons why the executable file might be covered by
* the GNU General Public License.
*
* Copyright 2007 Develer S.r.l. (http://www.develer.com/)
*
* -->
*
*
* \author Francesco Sacchi <batt@develer.com>
* \author Daniele Basile <asterix@develer.com>
*
* AT91SAM7 register definitions.
* This file is based on NUT/OS implementation. See license below.
*/
/*
* Copyright (C) 2006-2007 by egnite Software GmbH. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holders nor the names of
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
* SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* For additional information see http://www.ethernut.de/
*/
#ifndef AT91SAM7_H
#define AT91SAM7_H
#include <cfg/compiler.h>
#if CPU_ARM_SAM7X || CPU_ARM_SAM7S_LARGE
#define FLASH_BASE 0x100000UL
#define RAM_BASE 0x200000UL
#define TC_BASE 0xFFFA0000 ///< Timer/counter base address.
#define UDP_BASE 0xFFFB0000 ///< USB device port base address.
#define TWI_BASE 0xFFFB8000 ///< Two-wire interface base address.
#define USART0_BASE 0xFFFC0000 ///< USART 0 base address.
#define USART1_BASE 0xFFFC4000 ///< USART 1 base address.
#define PWMC_BASE 0xFFFCC000 ///< PWM controller base address.
#define SSC_BASE 0xFFFD4000 ///< Serial synchronous controller base address.
#define ADC_BASE 0xFFFD8000 ///< ADC base address.
#define AIC_BASE 0xFFFFF000 ///< AIC base address.
#define DBGU_BASE 0xFFFFF200 ///< DBGU base address.
#define PIOA_BASE 0xFFFFF400 ///< PIO A base address.
#define PMC_BASE 0xFFFFFC00 ///< PMC base address.
#define RSTC_BASE 0xFFFFFD00 ///< Resect controller register base address.
#define RTT_BASE 0xFFFFFD20 ///< Realtime timer base address.
#define PIT_BASE 0xFFFFFD30 ///< Periodic interval timer base address.
#define WDT_BASE 0xFFFFFD40 ///< Watch Dog register base address.
#define VREG_BASE 0xFFFFFD60 ///< Voltage regulator mode controller base address.
#define MC_BASE 0xFFFFFF00 ///< Memory controller base.
#if CPU_ARM_SAM7X
#define CAN_BASE 0xFFFD0000 ///< PWM controller base address.
#define EMAC_BASE 0xFFFDC000 ///< Ethernet MAC address.
#define SPI0_BASE 0xFFFE0000 ///< SPI0 base address.
#define SPI1_BASE 0xFFFE4000 ///< SPI1 base address.
#define PIOB_BASE 0xFFFFF600 ///< PIO base address.
#endif
#if CPU_ARM_SAM7S_LARGE
#define SPI_BASE 0xFFFE0000 ///< SPI0 base address.
#endif
#define PIO_HAS_MULTIDRIVER 1
#define PIO_HAS_PULLUP 1
#define PIO_HAS_PERIPHERALSELECT 1
#define PIO_HAS_OUTPUTWRITEENABLE 1
#define DBGU_HAS_PDC 1
#define SPI_HAS_PDC 1
#define SSC_HAS_PDC 1
#define USART_HAS_PDC 1
/* PDC registers */
#define PERIPH_RPR_OFF 0x100 ///< Receive Pointer Register.
#define PERIPH_RCR_OFF 0x104 ///< Receive Counter Register.
#define PERIPH_TPR_OFF 0x108 ///< Transmit Pointer Register.
#define PERIPH_TCR_OFF 0x10C ///< Transmit Counter Register.
#define PERIPH_RNPR_OFF 0x110 ///< Receive Next Pointer Register.
#define PERIPH_RNCR_OFF 0x114 ///< Receive Next Counter Register.
#define PERIPH_TNPR_OFF 0x118 ///< Transmit Next Pointer Register.
#define PERIPH_TNCR_OFF 0x11C ///< Transmit Next Counter Register.
#define PERIPH_PTCR_OFF 0x120 ///< PDC Transfer Control Register.
#define PERIPH_PTSR_OFF 0x124 ///< PDC Transfer Status Register.
#define PDC_RXTEN 0
#define PDC_RXTDIS 1
#define PDC_TXTEN 8
#define PDC_TXTDIS 9
#else
#error No base address register definition for selected ARM CPU
#endif
#if CPU_ARM_AT91SAM7S64
#define FLASH_MEM_SIZE 0x10000UL ///< Internal flash memory size
#define FLASH_PAGE_SIZE_BYTES 128 ///< Size of cpu flash memory page in bytes
#define FLASH_BANKS_NUM 1 ///< Number of flash banks
#define FLASH_SECTORS_NUM 16 ///< Number of flash sector
#define FLASH_PAGE_PER_SECTOR 32 ///< Number of page for sector
#elif CPU_ARM_AT91SAM7S128 || CPU_ARM_AT91SAM7X128
#define FLASH_MEM_SIZE 0x20000UL ///< Internal flash memory size
#define FLASH_PAGE_SIZE_BYTES 256 ///< Size of cpu flash memory page in bytes
#define FLASH_BANKS_NUM 1 ///< Number of flash banks
#define FLASH_SECTORS_NUM 8 ///< Number of flash sector
#define FLASH_PAGE_PER_SECTOR 64 ///< Number of page for sector
#elif CPU_ARM_AT91SAM7S256 || CPU_ARM_AT91SAM7X256
#define FLASH_MEM_SIZE 0x40000UL ///< Internal flash memory size
#define FLASH_PAGE_SIZE_BYTES 256 ///< Size of cpu flash memory page in bytes
#define FLASH_BANKS_NUM 1 ///< Number of flash banks
#define FLASH_SECTORS_NUM 16 ///< Number of flash sector
#define FLASH_PAGE_PER_SECTOR 64 ///< Number of page for sector
#elif CPU_ARM_AT91SAM7S512 || CPU_ARM_AT91SAM7X512
#define FLASH_MEM_SIZE 0x80000UL ///< Internal flash memory size
#define FLASH_PAGE_SIZE_BYTES 256 ///< Size of cpu flash memory page in bytes
#define FLASH_BANKS_NUM 2 ///< Number of flash banks
#define FLASH_SECTORS_NUM 32 ///< Number of flash sector
#define FLASH_PAGE_PER_SECTOR 64 ///< Number of page for sector
#else
#error Memory size definition for selected ARM CPU
#endif
#include "at91_aic.h"
#include "at91_pit.h"
#include "at91_pmc.h"
#include "at91_mc.h"
#include "at91_wdt.h"
#include "at91_rstc.h"
#include "at91_pio.h"
#include "at91_us.h"
#include "at91_dbgu.h"
#include "at91_tc.h"
#include "at91_adc.h"
#include "at91_pwm.h"
#include "at91_spi.h"
#include "at91_twi.h"
#include "at91_ssc.h"
#include "at91_emac.h"
//TODO: add other peripherals
/**
* Peripheral Identifiers and Interrupts
*\{
*/
#if CPU_ARM_SAM7X || CPU_ARM_SAM7S_LARGE
#define FIQ_ID 0 ///< Fast interrupt ID.
#define SYSC_ID 1 ///< System controller interrupt.
#define US0_ID 6 ///< USART 0 ID.
#define US1_ID 7 ///< USART 1 ID.
#define SSC_ID 8 ///< Synchronous serial controller ID.
#define TWI_ID 9 ///< Two-wire interface ID.
#define PWMC_ID 10 ///< PWM controller ID.
#define UDP_ID 11 ///< USB device port ID.
#define TC0_ID 12 ///< Timer 0 ID.
#define TC1_ID 13 ///< Timer 1 ID.
#define TC2_ID 14 ///< Timer 2 ID.
#define IRQ0_ID 30 ///< External interrupt 0 ID.
#define IRQ1_ID 31 ///< External interrupt 1 ID.
#if CPU_ARM_SAM7X
#define PIOA_ID 2 ///< Parallel A I/O controller ID.
#define PIOB_ID 3 ///< Parallel B I/O controller ID.
#define SPI0_ID 4 ///< Serial peripheral interface 0 ID.
#define SPI1_ID 5 ///< Serial peripheral interface 1 ID.
#define CAN_ID 15 ///< CAN controller ID.
#define EMAC_ID 16 ///< Ethernet MAC ID.
#define ADC_ID 17 ///< Analog to digital converter ID.
/* 18-29 Reserved */
#endif
#if CPU_ARM_SAM7S_LARGE
#define PIOA_ID 2 ///< Parallel I/O controller ID.
/* ID 3 is reserved */
#define ADC_ID 4 ///< Analog to digital converter ID.
#define SPI_ID 5 ///< Serial peripheral interface ID.
#define SPI0_ID SPI_ID ///< Alias
#endif
#else
#error No peripheral ID and interrupts definition for selected ARM CPU
#endif
/*\}*/
/**
* USART & DEBUG pin names
*\{
*/
#if CPU_ARM_SAM7S_LARGE
#define RXD0 5
#define TXD0 6
#define RXD1 21
#define TXD1 22
#define DTXD 10
#define DRXD 9
#elif CPU_ARM_SAM7X
#define RXD0 0 // PA0
#define TXD0 1 // PA1
#define RXD1 5 // PA5
#define TXD1 6 // PA6
#define DTXD 28 // PA28
#define DRXD 27 // PA27
#else
#error No USART & debug pin names definition for selected ARM CPU
#endif
/*\}*/
/**
* SPI pins name
*\{
*/
#if CPU_ARM_SAM7S_LARGE
#define SPI0_NPCS0 11 // Same as NSS pin.
#define SPI0_MISO 12
#define SPI0_MOSI 13
#define SPI0_SPCK 14
#elif CPU_ARM_SAM7X
#define SPI0_NPCS0 12 // Same as NSS pin. PA12
#define SPI0_NPCS1 13 // PA13
#define SPI0_NPCS2 14 // PA14
#define SPI0_NPCS3 15 // PA15
#define SPI0_MISO 16 // PA16
#define SPI0_MOSI 17 // PA17
#define SPI0_SPCK 18 // PA18
#define SPI1_NPCS0 21 // Same as NSS pin. PA21
#define SPI1_NPCS1 25 // PA25
#define SPI1_NPCS2 26 // PA26
#define SPI1_NPCS3 29 // PA29
#define SPI1_MISO 24 // PA24
#define SPI1_MOSI 23 // PA23
#define SPI1_SPCK 22 // PA22
#else
#error No SPI pins name definition for selected ARM CPU
#endif
/*\}*/
/**
* SSC pins name
*\{
*/
#if CPU_ARM_SAM7S_LARGE
#define SSC_TF 15 // PA15
#define SSC_TK 16 // PA16
#define SSC_TD 17 // PA17
#define SSC_RD 18 // PA18
#define SSC_RK 19 // PA19
#define SSC_RF 20 // PA20
#elif CPU_ARM_SAM7X
#define SSC_TF 21 // PA21
#define SSC_TK 22 // PA22
#define SSC_TD 23 // PA23
#define SSC_RD 24 // PA24
#define SSC_RK 25 // PA25
#define SSC_RF 26 // PA26
#else
#error No SSC pins name definition for selected ARM CPU
#endif
/*\}*/
/**
* Timer counter pins definition.
*\{
*/
#if CPU_ARM_SAM7X
#define TIOA0 23 // PB23
#define TIOB0 24 // PB24
#define TIOA1 25 // PB25
#define TIOB1 26 // PB26
#define TIOA2 27 // PB27
#define TIOB2 28 // PB28
#define TIO_PIO_PDR PIOB_PDR
#define TIO_PIO_ABSR PIOB_ASR
#elif CPU_ARM_SAM7S_LARGE
#define TIOA0 0 // PA0
#define TIOB0 1 // PA1
#define TIOA1 15 // PA15
#define TIOB1 16 // PA16
#define TIOA2 26 // PA26
#define TIOB2 27 // PA27
#define TIO_PIO_PDR PIOA_PDR
#define TIO_PIO_ABSR PIOA_BSR
#else
#error No Timer Counter names of pins definition for selected ARM CPU
#endif
/*\}*/
/**
* PWM pins definition.
*\{
*/
#if CPU_ARM_SAM7X
#define PWM0 19 // PB19
#define PWM1 20 // PB20
#define PWM2 21 // PB21
#define PWM3 22 // PB22
#define PWM_PIO_PDR PIOB_PDR
#define PWM_PIO_PER PIOB_PER
#define PWM_PIO_CODR PIOB_CODR
#define PWM_PIO_OER PIOB_OER
#define PWM_PIO_ABSR PIOB_ASR
#elif CPU_ARM_SAM7S_LARGE
#define PWM0 11 // PA11
#define PWM1 12 // PA12
#define PWM2 13 // PA13
#define PWM3 14 // PA14
#define PWM_PIO_PDR PIOA_PDR
#define PWM_PIO_PER PIOA_PER
#define PWM_PIO_CODR PIOA_CODR
#define PWM_PIO_OER PIOA_OER
#define PWM_PIO_ABSR PIOA_BSR
#else
#error No PWM names of pins definition for selected ARM CPU
#endif
/*\}*/
/**
* TWI pins definition.
*\{
*/
#if CPU_ARM_SAM7X
#define TWD 10
#define TWCK 11
#elif CPU_ARM_SAM7S_LARGE
#define TWD 3 //PA3
#define TWCK 4 //PA4
#else
#error No TWI names of pins definition for selected ARM CPU
#endif
/**
* ADC pins definition.
*\{
*/
#if CPU_ARM_SAM7X
#define ADTRG 18 // PB18
#define AD0 23 // PB27
#define AD1 24 // PB28
#define AD2 25 // PB29
#define AD3 26 // PB30
#elif CPU_ARM_SAM7S_LARGE
#define ADTRG 18 // PA8
#define AD0 0 // PA17
#define AD1 1 // PA18
#define AD2 15 // PA19
#define AD3 16 // PA20
#else
#error No ADC names of pins definition for selected ARM CPU
#endif
/*\}*/
#endif /* AT91SAM7_H */

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