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Before PLL algo adjust

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This commit is contained in:
Mark Qvist 2014-04-08 18:08:58 +02:00
parent f42f6d8bae
commit 65820627ec
3 changed files with 4 additions and 4 deletions
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4
Modem/afsk.c
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@ -83,7 +83,7 @@ INLINE uint8_t sinSample(uint16_t i) {
#define PHASE_BITS 8
#define PHASE_INC 1 // FIXME: originally 1
#define PHASE_MAX (SAMPLESPERBIT * PHASE_BITS)
#define PHASE_THRESHOLD (PHASE_MAX / 4) + (PHASE_MAX / 8) // FIXME: originally /2
#define PHASE_THRESHOLD (PHASE_MAX / 4) // FIXME: originally /2
// Modulation constants
#define MARK_FREQ 1200
@ -348,7 +348,7 @@ void afsk_adc_isr(Afsk *afsk, int8_t currentSample) {
}
}
// We incroment our phase counter
// We increment our phase counter
afsk->currentPhase += PHASE_BITS;
// Check if we have reached the end of

2
Modem/main.c
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@ -103,7 +103,7 @@ int main(void)
// and the byte is not a "transmit" (newline) character,
// we should store it for transmission.
if ((serialLen < MP1_MAX_FRAME_LENGTH) && (sbyte != 138)) {
kprintf("Byte: %d\n", sbyte);
//kprintf("Byte: %d\n", sbyte); // FIXME: delete
// Put the read byte into the buffer;
serialBuffer[serialLen] = sbyte;
// Increment the read length counter

2
buildrev.h
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@ -1,2 +1,2 @@
#define VERS_BUILD 477
#define VERS_BUILD 480
#define VERS_HOST "vixen"