mirror of
https://github.com/tillitis/tillitis-key1.git
synced 2025-12-16 17:14:21 -05:00
c35e7680ea
Silence lint on intentional combinatinal loops
Use better instance names, and a single lint pragma for all macros
Remove unused pointer update signals
Silence lint on wires where not all bits are used
Change fw_app_mode to be an input port to allow access control
Remove redundant, unused wire mem_busy
Add lint pragma to ignore debug register only enabled by a define
Remove clk and reset_n ports from the ROM
Adding note and lint pragma for rom address width
Fix incorrect register widths in uart_core
Assign all 16 bits in LUT config
Silence lint warnings on macro instances
Correct bit extraction for core addresses to be eight bits wide
Correct the bit width of cdi_mem_we wire
Add specific output file for logging lint issues
Correct bit width of tmp_ready to match one bit ready port
113 lines
3.1 KiB
Verilog
113 lines
3.1 KiB
Verilog
//======================================================================
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//
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// clk_reset_gen.v
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// -----------
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// Clock and reset generator used in the Tillitis Key 1 design.
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// This module instantiate the internal SB_HFOSC clock source in the
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// Lattice ice40 UP device. It then connects it to the PLL, and
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// finally connects the output from the PLL to the global clock net.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2022 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module clk_reset_gen #(parameter RESET_CYCLES = 200)
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(
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output wire clk,
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output wire rst_n
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);
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//----------------------------------------------------------------
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// Registers with associated wires.
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//----------------------------------------------------------------
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reg [7 : 0] rst_ctr_reg = 8'h0;
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reg [7 : 0] rst_ctr_new;
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reg rst_ctr_we;
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reg rst_n_reg = 1'h0;
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reg rst_n_new;
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wire hfosc_clk;
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wire pll_clk;
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//----------------------------------------------------------------
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// Concurrent assignment.
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//----------------------------------------------------------------
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assign rst_n = rst_n_reg;
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//----------------------------------------------------------------
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// Core instantiations.
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//----------------------------------------------------------------
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/* verilator lint_off PINMISSING */
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// Use the FPGA internal High Frequency OSCillator as clock source.
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// 00: 48MHz, 01: 24MHz, 10: 12MHz, 11: 6MHz
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SB_HFOSC #(.CLKHF_DIV("0b10")
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) hfosc_inst (.CLKHFPU(1'b1),.CLKHFEN(1'b1),.CLKHF(hfosc_clk));
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// Use a PLL to generate a new clock frequency based on the HFOSC clock.
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SB_PLL40_CORE #(
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.FEEDBACK_PATH("SIMPLE"),
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.DIVR(4'b0000), // DIVR = 0
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.DIVF(7'b0101111), // DIVF = 47
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.DIVQ(3'b101), // DIVQ = 5
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.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
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) pll_inst (
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.RESETB(1'b1),
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.BYPASS(1'b0),
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.REFERENCECLK(hfosc_clk),
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.PLLOUTCORE(pll_clk)
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);
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// Use a Global Buffer to distribute the clock.
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SB_GB gb_inst (
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.USER_SIGNAL_TO_GLOBAL_BUFFER (pll_clk),
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.GLOBAL_BUFFER_OUTPUT (clk)
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);
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/* verilator lint_on PINMISSING */
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//----------------------------------------------------------------
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// reg_update.
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//----------------------------------------------------------------
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always @(posedge clk)
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begin : reg_update
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rst_n_reg <= rst_n_new;
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if (rst_ctr_we)
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rst_ctr_reg <= rst_ctr_new;
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end
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//----------------------------------------------------------------
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// rst_logic.
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//----------------------------------------------------------------
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always @*
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begin : rst_logic
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rst_n_new = 1'h1;
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rst_ctr_new = 8'h0;
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rst_ctr_we = 1'h0;
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if (rst_ctr_reg < RESET_CYCLES) begin
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rst_n_new = 1'h0;
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rst_ctr_new = rst_ctr_reg + 1'h1;
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rst_ctr_we = 1'h1;
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end
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end
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endmodule // reset_gen
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//======================================================================
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// EOF reset_gen.v
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//======================================================================
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