mirror of
https://github.com/tillitis/tillitis-key1.git
synced 2024-12-26 07:59:36 -05:00
00599549e3
Add API address to trigger system reset.
When written to will send system_reset signal
to the reset generator, which then perform a complete
reset cycle of the FPGA system.
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
153 lines
4.0 KiB
C
153 lines
4.0 KiB
C
/*
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* Tillitis TKey Memory Map
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*
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* Copyright (c) 2022, 2023, 2024 Tillitis AB
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* Note that this file is also included in at least qemu
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* (GPL-2.0-or-later) besides tillitis-key1 (GPL-2.0-only) and
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* tkey-libs (GPL-2.0-only) so it's licensed as GPL v2 or later.
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*/
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// clang-format off
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#ifndef TKEY_TK1_MEM_H
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#define TKEY_TK1_MEM_H
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/*
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The canonical location of this file is in:
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https://github.com/tillitis/tillitis-key1
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/hw/application_fpga/fw/tk1_mem.h
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The contents are derived from the Verilog code. For use by QEMU model,
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firmware, and apps.
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Memory map
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Top level prefix, the first 2 bits in a 32-bit address:
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name prefix address length
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--------------------------------------------------------
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ROM 0b00 30 bit address
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RAM 0b01 30 bit address
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Reserved 0b10
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MMIO 0b11 6 bits for core select, 24 bits rest
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Address Prefix, the first 8 bits in a 32-bit address:
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name prefix
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--------------------
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ROM 0x00
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RAM 0x40
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MMIO 0xc0
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MMIO TRNG 0xc0
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MMIO TIMER 0xc1
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MMIO UDS 0xc2
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MMIO UART 0xc3
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MMIO TOUCH 0xc4
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MMIO FW_RAM 0xd0
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MMIO QEMU 0xfe Not used in real hardware
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MMIO TK1 0xff
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*/
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#define TK1_ROM_BASE 0x00000000
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#define TK1_RAM_BASE 0x40000000
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#define TK1_RAM_SIZE 0x20000
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#define TK1_MMIO_BASE 0xc0000000
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#define TK1_MMIO_SIZE 0x3fffffff
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#define TK1_APP_MAX_SIZE 0x20000
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#define TK1_MMIO_FW_RAM_BASE 0xd0000000
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// FW_RAM is 2048 bytes
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#define TK1_MMIO_FW_RAM_SIZE 0x800
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#define TK1_MMIO_TRNG_BASE 0xc0000000
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#define TK1_MMIO_TRNG_STATUS 0xc0000024
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#define TK1_MMIO_TRNG_STATUS_READY_BIT 0
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#define TK1_MMIO_TRNG_ENTROPY 0xc0000080
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#define TK1_MMIO_TIMER_BASE 0xc1000000
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#define TK1_MMIO_TIMER_CTRL 0xc1000020
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#define TK1_MMIO_TIMER_CTRL_START_BIT 0
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#define TK1_MMIO_TIMER_CTRL_STOP_BIT 1
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#define TK1_MMIO_TIMER_STATUS 0xc1000024
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#define TK1_MMIO_TIMER_STATUS_RUNNING_BIT 0
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#define TK1_MMIO_TIMER_PRESCALER 0xc1000028
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#define TK1_MMIO_TIMER_TIMER 0xc100002c
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#define TK1_MMIO_UDS_BASE 0xc2000000
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#define TK1_MMIO_UDS_FIRST 0xc2000040
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#define TK1_MMIO_UDS_LAST 0xc200005c
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#define TK1_MMIO_UART_BASE 0xc3000000
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#define TK1_MMIO_UART_BIT_RATE 0xc3000040
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#define TK1_MMIO_UART_DATA_BITS 0xc3000044
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#define TK1_MMIO_UART_STOP_BITS 0xc3000048
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#define TK1_MMIO_UART_RX_STATUS 0xc3000080
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#define TK1_MMIO_UART_RX_DATA 0xc3000084
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#define TK1_MMIO_UART_RX_BYTES 0xc3000088
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#define TK1_MMIO_UART_TX_STATUS 0xc3000100
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#define TK1_MMIO_UART_TX_DATA 0xc3000104
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#define TK1_MMIO_TOUCH_BASE 0xc4000000
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#define TK1_MMIO_TOUCH_STATUS 0xc4000024
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#define TK1_MMIO_TOUCH_STATUS_EVENT_BIT 0
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// This only exists in QEMU, not real hardware
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#define TK1_MMIO_QEMU_BASE 0xfe000000
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#define TK1_MMIO_QEMU_DEBUG 0xfe001000
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#define TK1_MMIO_TK1_BASE 0xff000000
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#define TK1_MMIO_TK1_NAME0 0xff000000
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#define TK1_MMIO_TK1_NAME1 0xff000004
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#define TK1_MMIO_TK1_VERSION 0xff000008
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#define TK1_MMIO_TK1_SWITCH_APP 0xff000020
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#define TK1_MMIO_TK1_LED 0xff000024
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#define TK1_MMIO_TK1_LED_R_BIT 2
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#define TK1_MMIO_TK1_LED_G_BIT 1
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#define TK1_MMIO_TK1_LED_B_BIT 0
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#define TK1_MMIO_TK1_GPIO 0xff000028
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#define TK1_MMIO_TK1_GPIO1_BIT 0
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#define TK1_MMIO_TK1_GPIO2_BIT 1
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#define TK1_MMIO_TK1_GPIO3_BIT 2
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#define TK1_MMIO_TK1_GPIO4_BIT 3
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#define TK1_MMIO_TK1_APP_ADDR 0xff000030
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#define TK1_MMIO_TK1_APP_SIZE 0xff000034
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#define TK1_MMIO_TK1_BLAKE2S 0xff000040
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#define TK1_MMIO_TK1_CDI_FIRST 0xff000080
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#define TK1_MMIO_TK1_CDI_LAST 0xff00009c
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#define TK1_MMIO_TK1_UDI_FIRST 0xff0000c0
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#define TK1_MMIO_TK1_UDI_LAST 0xff0000c4
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// Deprecated - use _ADDR_RAND instead
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#define TK1_MMIO_TK1_RAM_ASLR 0xff000100
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#define TK1_MMIO_TK1_RAM_ADDR_RAND 0xff000100
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// Deprecated - use _DATA_RAND instead
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#define TK1_MMIO_TK1_RAM_SCRAMBLE 0xff000104
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#define TK1_MMIO_TK1_RAM_DATA_RAND 0xff000104
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#define TK1_MMIO_TK1_CPU_MON_CTRL 0xff000180
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#define TK1_MMIO_TK1_CPU_MON_FIRST 0xff000184
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#define TK1_MMIO_TK1_CPU_MON_LAST 0xff000188
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#define TK1_MMIO_TK1_SYSTEM_RESET 0xff0001C0
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#define TK1_MMIO_TK1_SPI_EN 0xff000200
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#define TK1_MMIO_TK1_SPI_XFER 0xff000204
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#define TK1_MMIO_TK1_SPI_DATA 0xff000208
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#endif
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