mirror of
https://github.com/tillitis/tillitis-key1.git
synced 2024-10-01 01:45:38 -04:00
155 lines
3.5 KiB
Verilog
155 lines
3.5 KiB
Verilog
module top (
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/* verilator lint_off UNUSED */
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input RX,
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/* verilator lint_on UNUSED */
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output reg TX,
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input RTS,
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output CTS,
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output APP_GPIO1,
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output APP_GPIO2,
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output APP_GPIO3,
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output APP_GPIO4,
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input TOUCH_EVENT,
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output RGB0,
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output RGB1,
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output RGB2
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);
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//############ Clock / Reset ############################################
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wire clk;
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// Configure the HFOSC
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SB_HFOSC #(
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.CLKHF_DIV("0b01") // 00: 48MHz, 01: 24MHz, 10: 12MHz, 11: 6MHz
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) u_hfosc (
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.CLKHFPU(1'b1),
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.CLKHFEN(1'b1),
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.CLKHF(clk)
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);
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//############ Extra I/O test #####################################
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reg [4:0] pintest;
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initial begin
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pintest = 5'h01;
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end
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assign {CTS, APP_GPIO1, APP_GPIO2, APP_GPIO3, APP_GPIO4} = pintest;
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always @(posedge RTS) begin
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case(pintest)
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5'h1: pintest <= 5'h2;
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5'h2: pintest <= 5'h4;
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5'h4: pintest <= 5'h8;
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5'h8: pintest <= 5'h10;
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default: pintest <= 5'h01;
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endcase
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end
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//############ LED pwm ##################################################
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reg [24:0] led_divider;
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reg [2:0] led_states;
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initial begin
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led_divider = 25'd0;
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end
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always @(posedge clk) begin
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led_divider <= led_divider + 1;
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case(led_divider[24:23])
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2'h0: led_states <= 3'b100;
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2'h1: led_states <= 3'b010;
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2'h2: led_states <= 3'b001;
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2'h3: led_states <= 3'b111;
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endcase
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end
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SB_RGBA_DRV #(
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.CURRENT_MODE("0b1"), // half-current mode
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.RGB0_CURRENT("0b000001"), // 2 mA
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.RGB1_CURRENT("0b000001"), // 2 mA
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.RGB2_CURRENT("0b000001") // 2 mA
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) RGBA_DRV (
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.RGB0(RGB0),
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.RGB1(RGB1),
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.RGB2(RGB2),
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.RGBLEDEN(~TOUCH_EVENT),
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.RGB0PWM(led_states[2]),
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.RGB1PWM(led_states[1]),
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.RGB2PWM(led_states[0]),
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.CURREN(1'b1)
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);
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//############ Serial output ############################################
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reg [24:0] ticks; // about once a second
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reg [7:0] touch_count;
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reg [7:0] report_count;
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initial begin
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ticks = 25'd0;
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touch_count = 8'd0;
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report_count = 8'd0;
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end
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reg [19:0] uart_data;
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reg [7:0] uart_bits_left;
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reg [13:0] uart_count;
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initial begin
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TX = 1'b1;
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end
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reg touch_last;
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reg tx_last;
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initial begin
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tx_last = 1;
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end
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always @(posedge clk) begin
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// Sample + count touch events
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touch_last <= TOUCH_EVENT;
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tx_last <= TX;
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if ((touch_last == 0) && (TOUCH_EVENT == 1)) begin
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touch_count <= touch_count + 1;
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end
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// Create a ~1s delay between touch count reports
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ticks <= ticks + 1;
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TX <= uart_data[0];
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// Periodically report the touch count
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//if (ticks == 0) begin
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if((TX == 0) && (tx_last == 1) && (uart_bits_left == 0)) begin
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// LSB first: start bit, report count, stop bit, start bit, touch count, stop bit
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uart_data <= {1'b1, touch_count[7:0], 1'b0, 1'b1, report_count[7:0], 1'b0};
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uart_bits_left <= 8'd19;
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uart_count <= 14'd2500;
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report_count <= report_count + 1;
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end
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if (uart_bits_left > 0) begin
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uart_count <= uart_count - 1;
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if(uart_count == 0) begin
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uart_data <= {1'b1, uart_data[19:1]};
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uart_bits_left <= uart_bits_left - 1;
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uart_count <= 14'd2500;
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end
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end
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end
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endmodule
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