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tillitis-key/hw/application_fpga
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Michael Cardell Widerkrantz f386cec1ed
fw: Add destination buffer size to read() 
Signed-off-by: Daniel Lublin <daniel@lublin.se>
2023-03-14 10:25:00 +01:00
..
core
Update fw ram last address to match new mem size
2023-03-08 13:31:45 +01:00
data
Rename to TK1
2022-10-26 09:20:02 +02:00
fw
fw: Add destination buffer size to read()
2023-03-14 10:25:00 +01:00
rtl
bank1 access should also be disabled by default.
2023-03-13 12:43:07 +01:00
tb
Rename to TK1
2022-10-26 09:20:02 +02:00
tools
Correct to new path
2023-01-13 15:42:46 +01:00
config.vlt
Config verilator lint to ignore known 3rd-party warnings; let warnings be fatal
2023-03-01 13:37:31 +01:00
Makefile
Config verilator lint to ignore known 3rd-party warnings; let warnings be fatal
2023-03-01 13:37:31 +01:00