Joachim Strömbergson e961f46e79

Update Verilog version to 2005 for linting ...

Signed-off-by: Joachim Strömbergson <joachim@assured.se>

2024-04-24 08:44:08 +02:00

..

core

Update Verilog version to 2005 for linting

2024-04-24 08:44:08 +02:00

data

Change name of pin constraint file to match tk1 pcb

2023-07-04 09:04:29 +02:00

fw

fw: Remove unused header includes

2024-03-26 13:09:06 +01:00

rtl

Clean up code and silence warnings after linting

2024-03-20 16:39:53 +01:00

tb

Rename to TK1

2022-10-26 09:20:02 +02:00

tools

hw/tool: UDI/UDS storage

2024-04-03 11:27:00 +02:00

application_fpga.bin.sha256

Update hash of bitstream and firmware

2024-03-26 13:09:06 +01:00

config.vlt

Config verilator lint to ignore known 3rd-party warnings; let warnings be fatal

2023-03-01 13:37:31 +01:00

firmware.bin.sha512

Update hash of bitstream and firmware

2024-03-26 13:09:06 +01:00

Makefile

Change filename personalize.py to patch_uds_udi.py

2024-03-26 13:07:11 +01:00