mirror of
https://github.com/tillitis/tillitis-key1.git
synced 2024-07-12 06:12:22 +00:00
655 lines
19 KiB
Verilog
655 lines
19 KiB
Verilog
//======================================================================
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//
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// tb_tk1.v
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// --------
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// Testbench for the TK1 core.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2023 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module tb_tk1();
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//----------------------------------------------------------------
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// Internal constant and parameter definitions.
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//----------------------------------------------------------------
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parameter DEBUG = 1;
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parameter CLK_HALF_PERIOD = 1;
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parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
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localparam ADDR_NAME0 = 8'h00;
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localparam ADDR_NAME1 = 8'h01;
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localparam ADDR_VERSION = 8'h02;
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localparam ADDR_SWITCH_APP = 8'h08;
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localparam ADDR_LED = 8'h09;
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localparam LED_R_BIT = 2;
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localparam LED_G_BIT = 1;
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localparam LED_B_BIT = 0;
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localparam ADDR_GPIO = 8'h0a;
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localparam GPIO1_BIT = 0;
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localparam GPIO2_BIT = 1;
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localparam GPIO3_BIT = 2;
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localparam GPIO4_BIT = 3;
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localparam ADDR_APP_START = 8'h0c;
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localparam ADDR_APP_SIZE = 8'h0d;
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localparam ADDR_BLAKE2S = 8'h10;
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localparam ADDR_CDI_FIRST = 8'h20;
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localparam ADDR_CDI_LAST = 8'h27;
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localparam ADDR_UDI_FIRST = 8'h30;
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localparam ADDR_UDI_LAST = 8'h31;
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localparam ADDR_RAM_ASLR = 8'h40;
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localparam ADDR_RAM_SCRAMBLE = 8'h41;
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localparam ADDR_CPU_MON_CTRL = 8'h60;
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localparam ADDR_CPU_MON_FIRST = 8'h61;
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localparam ADDR_CPU_MON_LAST = 8'h62;
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//----------------------------------------------------------------
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// Register and Wire declarations.
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//----------------------------------------------------------------
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reg [31 : 0] cycle_ctr;
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reg [31 : 0] error_ctr;
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reg [31 : 0] tc_ctr;
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reg tb_monitor;
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reg tb_clk;
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reg tb_reset_n;
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reg tb_cpu_trap;
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wire tb_fw_app_mode;
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reg [31 : 0] tb_cpu_addr;
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reg tb_cpu_instr;
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reg tb_cpu_valid;
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wire tb_force_trap;
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wire [14 : 0] tb_ram_aslr;
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wire [31 : 0] tb_ram_scramble;
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wire tb_led_r;
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wire tb_led_g;
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wire tb_led_b;
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reg tb_gpio1;
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reg tb_gpio2;
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wire tb_gpio3;
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wire tb_gpio4;
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reg tb_cs;
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reg tb_we;
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reg [7 : 0] tb_address;
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reg [31 : 0] tb_write_data;
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wire [31 : 0] tb_read_data;
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wire tb_ready;
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//----------------------------------------------------------------
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// Device Under Test.
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//----------------------------------------------------------------
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tk1 dut(
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.clk(tb_clk),
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.reset_n(tb_reset_n),
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.cpu_trap(tb_cpu_trap),
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.fw_app_mode(tb_fw_app_mode),
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.cpu_addr(tb_cpu_addr),
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.cpu_instr(tb_cpu_instr),
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.cpu_valid(tb_cpu_valid),
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.force_trap(tb_force_trap),
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.ram_aslr(tb_ram_aslr),
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.ram_scramble(tb_ram_scramble),
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.led_r(tb_led_r),
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.led_g(tb_led_g),
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.led_b(tb_led_b),
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.gpio1(tb_gpio1),
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.gpio2(tb_gpio2),
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.gpio3(tb_gpio3),
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.gpio4(tb_gpio4),
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.cs(tb_cs),
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.we(tb_we),
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.address(tb_address),
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.write_data(tb_write_data),
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.read_data(tb_read_data),
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.ready(tb_ready)
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);
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//----------------------------------------------------------------
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// clk_gen
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//
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// Always running clock generator process.
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//----------------------------------------------------------------
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always
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begin : clk_gen
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#CLK_HALF_PERIOD;
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tb_clk = !tb_clk;
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end // clk_gen
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//----------------------------------------------------------------
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// sys_monitor()
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//
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// An always running process that creates a cycle counter and
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// conditionally displays information about the DUT.
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//----------------------------------------------------------------
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always
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begin : sys_monitor
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cycle_ctr = cycle_ctr + 1;
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#(CLK_PERIOD);
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if (tb_monitor)
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begin
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dump_dut_state();
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end
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end
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//----------------------------------------------------------------
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// dump_dut_state()
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//
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// Dump the state of the dump when needed.
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//----------------------------------------------------------------
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task dump_dut_state;
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begin : dump_dut_state
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$display("State of DUT at cycle: %08d", cycle_ctr);
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$display("------------");
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$display("Inputs and outputs:");
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$display("tb_cpu_trap: 0x%1x, fw_app_mode: 0x%1x", tb_cpu_trap, tb_fw_app_mode);
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$display("cpu_addr: 0x%08x, cpu_instr: 0x%1x, cpu_valid: 0x%1x, force_tap: 0x%1x",
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tb_cpu_addr, tb_cpu_instr, tb_cpu_valid, tb_force_trap);
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$display("ram_aslr: 0x%08x, ram_scramble: 0x%08x", tb_ram_aslr, tb_ram_scramble);
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$display("led_r: 0x%1x, led_g: 0x%1x, led_b: 0x%1x", tb_led_r, tb_led_g, tb_led_b);
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$display("ready: 0x%1x, cs: 0x%1x, we: 0x%1x, address: 0x%02x", tb_ready, tb_cs, tb_we, tb_address);
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$display("write_data: 0x%08x, read_data: 0x%08x", tb_write_data, tb_read_data);
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$display("");
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$display("Internal state:");
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$display("tmp_read_ready: 0x%1x, tmp_read_data: 0x%08x", dut.tmp_ready, dut.tmp_read_data);
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$display("");
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$display("");
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end
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endtask // dump_dut_state
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//----------------------------------------------------------------
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// reset_dut()
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//
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// Toggle reset to put the DUT into a well known state.
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//----------------------------------------------------------------
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task reset_dut;
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begin
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$display("--- Toggle reset.");
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tb_reset_n = 0;
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#(2 * CLK_PERIOD);
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tb_reset_n = 1;
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end
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endtask // reset_dut
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//----------------------------------------------------------------
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// display_test_result()
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//
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// Display the accumulated test results.
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//----------------------------------------------------------------
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task display_test_result;
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begin
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if (error_ctr == 0)
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begin
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$display("--- All %02d test cases completed successfully", tc_ctr);
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end
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else
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begin
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$display("--- %02d tests completed - %02d test cases did not complete successfully.",
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tc_ctr, error_ctr);
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end
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end
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endtask // display_test_result
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//----------------------------------------------------------------
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// init_sim()
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//
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// Initialize all counters and testbed functionality as well
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// as setting the DUT inputs to defined values.
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//----------------------------------------------------------------
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task init_sim;
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begin
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cycle_ctr = 0;
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error_ctr = 0;
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tc_ctr = 0;
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tb_monitor = 0;
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tb_clk = 1'h0;
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tb_reset_n = 1'h1;
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tb_cpu_addr = 32'h0;
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tb_cpu_instr = 1'h0;
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tb_cpu_valid = 1'h0;
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tb_cpu_trap = 1'h0;
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tb_gpio1 = 1'h0;
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tb_gpio2 = 1'h0;
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tb_cs = 1'h0;
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tb_we = 1'h0;
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tb_address = 8'h0;
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tb_write_data = 32'h0;
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end
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endtask // init_sim
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//----------------------------------------------------------------
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// write_word()
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//
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// Write the given word to the DUT using the DUT interface.
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//----------------------------------------------------------------
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task write_word(input [11 : 0] address,
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input [31 : 0] word);
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begin
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if (DEBUG)
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begin
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$display("--- Writing 0x%08x to 0x%02x.", word, address);
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$display("");
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end
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tb_address = address;
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tb_write_data = word;
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tb_cs = 1;
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tb_we = 1;
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#(2 * CLK_PERIOD);
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tb_cs = 0;
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tb_we = 0;
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end
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endtask // write_word
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//----------------------------------------------------------------
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// read_word()
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//
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// Read a data word from the given address in the DUT.
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// the word read will be available in the global variable
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// read_data.
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//----------------------------------------------------------------
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task read_word(input [11 : 0] address, input [31 : 0] expected);
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begin : read_word
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reg [31 : 0] read_data;
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tb_address = address;
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tb_cs = 1'h1;
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#(CLK_HALF_PERIOD);
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read_data = tb_read_data;
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#(CLK_HALF_PERIOD);
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tb_cs = 1'h0;
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if (DEBUG)
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begin
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if (read_data == expected) begin
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$display("--- Reading 0x%08x from 0x%02x.", read_data, address);
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end else begin
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$display("--- Error: Got 0x%08x when reading from 0x%02x, expected 0x%08x",
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read_data, address, expected);
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error_ctr = error_ctr + 1;
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end
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$display("");
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end
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end
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endtask // read_word
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//----------------------------------------------------------------
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// test1()
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// Read out name and version.
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//----------------------------------------------------------------
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task test1;
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begin
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tc_ctr = tc_ctr + 1;
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$display("");
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$display("--- test1: Read out name and version started.");
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read_word(ADDR_NAME0, 32'h746B3120);
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read_word(ADDR_NAME1, 32'h6d6b6466);
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read_word(ADDR_VERSION, 32'h00000005);
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$display("--- test1: completed.");
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$display("");
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end
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endtask // test1
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//----------------------------------------------------------------
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// test2()
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// Read out UDI.
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//----------------------------------------------------------------
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task test2;
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begin
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tc_ctr = tc_ctr + 1;
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$display("");
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$display("--- test2: Read out UDI started.");
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read_word(ADDR_UDI_FIRST, 32'h00010203);
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read_word(ADDR_UDI_LAST, 32'h04050607);
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$display("--- test2: completed.");
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$display("");
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end
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endtask // test2
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//----------------------------------------------------------------
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// test3()
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// Read out CDI.
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//----------------------------------------------------------------
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task test3;
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begin
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tc_ctr = tc_ctr + 1;
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$display("");
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$display("--- test3: Write and read CDI started.");
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$display("--- test3: Write CDI.");
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write_word(ADDR_CDI_FIRST + 0, 32'hf0f1f2f3);
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write_word(ADDR_CDI_FIRST + 1, 32'he0e1e2e3);
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write_word(ADDR_CDI_FIRST + 2, 32'hd0d1d2d3);
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write_word(ADDR_CDI_FIRST + 3, 32'hc0c1c2c3);
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write_word(ADDR_CDI_FIRST + 4, 32'ha0a1a2a3);
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write_word(ADDR_CDI_FIRST + 5, 32'h90919293);
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write_word(ADDR_CDI_FIRST + 6, 32'h80818283);
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write_word(ADDR_CDI_FIRST + 7, 32'h70717273);
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$display("--- test3: Read CDI.");
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read_word(ADDR_CDI_FIRST + 0, 32'hf0f1f2f3);
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read_word(ADDR_CDI_FIRST + 1, 32'he0e1e2e3);
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read_word(ADDR_CDI_FIRST + 2, 32'hd0d1d2d3);
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read_word(ADDR_CDI_FIRST + 3, 32'hc0c1c2c3);
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read_word(ADDR_CDI_FIRST + 4, 32'ha0a1a2a3);
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read_word(ADDR_CDI_FIRST + 5, 32'h90919293);
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read_word(ADDR_CDI_FIRST + 6, 32'h80818283);
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read_word(ADDR_CDI_LAST + 0, 32'h70717273);
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$display("--- test3: Switch to app mode.");
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write_word(ADDR_SWITCH_APP, 32'hdeadbeef);
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$display("--- test3: Try to write CDI again.");
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write_word(ADDR_CDI_FIRST + 0, 32'hfffefdfc);
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write_word(ADDR_CDI_FIRST + 1, 32'hefeeedec);
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write_word(ADDR_CDI_FIRST + 2, 32'hdfdedddc);
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write_word(ADDR_CDI_FIRST + 3, 32'hcfcecdcc);
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write_word(ADDR_CDI_FIRST + 4, 32'hafaeadac);
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write_word(ADDR_CDI_FIRST + 5, 32'h9f9e9d9c);
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write_word(ADDR_CDI_FIRST + 6, 32'h8f8e8d8c);
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write_word(ADDR_CDI_FIRST + 7, 32'h7f7e7d7c);
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$display("--- test3: Read CDI again.");
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read_word(ADDR_CDI_FIRST + 0, 32'hf0f1f2f3);
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read_word(ADDR_CDI_FIRST + 1, 32'he0e1e2e3);
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read_word(ADDR_CDI_FIRST + 2, 32'hd0d1d2d3);
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read_word(ADDR_CDI_FIRST + 3, 32'hc0c1c2c3);
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read_word(ADDR_CDI_FIRST + 4, 32'ha0a1a2a3);
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read_word(ADDR_CDI_FIRST + 5, 32'h90919293);
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read_word(ADDR_CDI_FIRST + 6, 32'h80818283);
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read_word(ADDR_CDI_LAST + 0, 32'h70717273);
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$display("--- test3: completed.");
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$display("");
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end
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endtask // test3
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//----------------------------------------------------------------
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// test4()
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// Write and read blake2s entry point.
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//----------------------------------------------------------------
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task test4;
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begin
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tc_ctr = tc_ctr + 1;
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$display("");
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$display("--- test4: Write and read blake2s entry point in fw mode started.");
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$display("--- test4: Reset DUT to switch to fw mode.");
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reset_dut();
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$display("--- test4: Write Blake2s entry point.");
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write_word(ADDR_BLAKE2S, 32'hcafebabe);
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$display("--- test4: Read Blake2s entry point.");
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read_word(ADDR_BLAKE2S, 32'hcafebabe);
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$display("--- test4: Switch to app mode.");
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write_word(ADDR_SWITCH_APP, 32'hf00ff00f);
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$display("--- test4: Write Blake2s entry point again.");
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write_word(ADDR_BLAKE2S, 32'hdeadbeef);
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$display("--- test4: Read Blake2s entry point again");
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read_word(ADDR_BLAKE2S, 32'hcafebabe);
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$display("--- test4: completed.");
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$display("");
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end
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endtask // test4
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//----------------------------------------------------------------
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// test5()
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// Write and read APP start address end size.
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//----------------------------------------------------------------
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task test5;
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begin
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tc_ctr = tc_ctr + 1;
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$display("");
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$display("--- test5: Write and read app start and size in fw mode started.");
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$display("--- test5: Reset DUT to switch to fw mode.");
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reset_dut();
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$display("--- test5: Write app start address and size.");
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write_word(ADDR_APP_START, 32'h13371337);
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write_word(ADDR_APP_SIZE, 32'h47114711);
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$display("--- test5: Read app start address and size.");
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read_word(ADDR_APP_START, 32'h13371337);
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read_word(ADDR_APP_SIZE, 32'h47114711);
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$display("--- test5: Switch to app mode.");
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write_word(ADDR_SWITCH_APP, 32'hf000000);
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$display("--- test5: Write app start address and size again.");
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write_word(ADDR_APP_START, 32'hdeadbeef);
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write_word(ADDR_APP_SIZE, 32'hf00ff00f);
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$display("--- test5: Read app start address and size.");
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read_word(ADDR_APP_START, 32'h13371337);
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read_word(ADDR_APP_SIZE, 32'h47114711);
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$display("--- test5: completed.");
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$display("");
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end
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endtask // test5
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//----------------------------------------------------------------
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// test6()
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// Write and RAM scrambling in fw mode.
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//----------------------------------------------------------------
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task test6;
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begin
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tc_ctr = tc_ctr + 1;
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$display("");
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$display("--- test6: Write RAM scrambling in fw mode.");
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$display("--- test6: Reset DUT to switch to fw mode.");
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reset_dut();
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$display("--- test6: Write RAM ASLR and RAM SCRAMBLE.");
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write_word(ADDR_RAM_ASLR, 32'h13371337);
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write_word(ADDR_RAM_SCRAMBLE, 32'h47114711);
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$display("--- test6: Check value in dut RAM ASLR and SCRAMBLE registers.");
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$display("--- test6: ram_aslr_reg: 0x%04x, ram_scramble_reg: 0x%08x", dut.ram_aslr_reg, dut.ram_scramble_reg);
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$display("--- test6: Switch to app mode.");
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write_word(ADDR_SWITCH_APP, 32'hf000000);
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$display("--- test6: Write RAM ASLR and SCRAMBLE again.");
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write_word(ADDR_RAM_ASLR, 32'hdeadbeef);
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write_word(ADDR_RAM_SCRAMBLE, 32'hf00ff00f);
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$display("--- test6: Check value in dut RAM ASLR and SCRAMBLE registers.");
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$display("--- test6: ram_aslr_reg: 0x%04x, ram_scramble_reg: 0x%08x", dut.ram_aslr_reg, dut.ram_scramble_reg);
|
|
|
|
$display("--- test6: completed.");
|
|
$display("");
|
|
end
|
|
endtask // test6
|
|
|
|
|
|
//----------------------------------------------------------------
|
|
// test7()
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|
// LED control.
|
|
//----------------------------------------------------------------
|
|
task test7;
|
|
begin
|
|
tc_ctr = tc_ctr + 1;
|
|
|
|
$display("");
|
|
$display("--- test7: LED control started.");
|
|
|
|
$display("--- test7: LEDs R: 0x%1x, G: 0x%1x, B: 0x%1x", tb_led_r, tb_led_g, tb_led_g);
|
|
$display("--- test7: Writing to LED control address to invert LED output.");
|
|
write_word(ADDR_LED, 32'h0);
|
|
$display("--- test7: LEDs R: 0x%1x, G: 0x%1x, B: 0x%1x", tb_led_r, tb_led_g, tb_led_g);
|
|
|
|
$display("--- test7: completed.");
|
|
$display("");
|
|
end
|
|
endtask // test7
|
|
|
|
|
|
//----------------------------------------------------------------
|
|
// test8()
|
|
// GPIO control.
|
|
//----------------------------------------------------------------
|
|
task test8;
|
|
begin
|
|
tc_ctr = tc_ctr + 1;
|
|
|
|
$display("");
|
|
$display("--- test8: GPIO control started.");
|
|
|
|
$display("--- test8: Set Inputs for GPIO 1 and 2 high.");
|
|
tb_gpio1 = 1'h1;
|
|
tb_gpio2 = 1'h1;
|
|
#(2 * CLK_PERIOD);
|
|
$display("--- test8: Check that we can read GPIO 1 and 2 as high.");
|
|
read_word(ADDR_GPIO, 32'h3);
|
|
|
|
$display("--- test8: Set GPIO 3 and 4 high by writing to the registers.");
|
|
write_word(ADDR_GPIO, 32'hf);
|
|
$display("--- test8: gpio3: 0x%1x, gpio4: 0x%1x", tb_gpio3, tb_gpio4);
|
|
|
|
$display("--- test8: completed.");
|
|
$display("");
|
|
end
|
|
endtask // test8
|
|
|
|
|
|
//----------------------------------------------------------------
|
|
// test9()
|
|
// EXE monitor control and detection.
|
|
//----------------------------------------------------------------
|
|
task test9;
|
|
begin
|
|
tc_ctr = tc_ctr + 1;
|
|
|
|
$display("");
|
|
$display("--- test9: EXE monitor control and detection started.");
|
|
|
|
$display("--- test9: Define and enable a memory area.");
|
|
write_word(ADDR_CPU_MON_FIRST, 32'h10000000);
|
|
write_word(ADDR_CPU_MON_LAST, 32'h20000000);
|
|
write_word(ADDR_CPU_MON_CTRL, 32'h1);
|
|
|
|
$display("--- test9: cpu_mon_first_reg: 0x%08x, cpu_mon_last_reg: 0x%08x",
|
|
dut.cpu_mon_first_reg, dut.cpu_mon_last_reg);
|
|
|
|
$display("--- test9: Try to redefine memory area after enabling monitor.");
|
|
write_word(ADDR_CPU_MON_FIRST, 32'hdeadbabe);
|
|
write_word(ADDR_CPU_MON_LAST, 32'hdeadcafe);
|
|
$display("--- test9: cpu_mon_first_reg: 0x%08x, cpu_mon_last_reg: 0x%08x",
|
|
dut.cpu_mon_first_reg, dut.cpu_mon_last_reg);
|
|
|
|
$display("--- test9: force_trap before illegal access: 0x%1x", tb_force_trap);
|
|
$display("--- test9: Creating an illegal access.");
|
|
|
|
tb_cpu_addr = 32'h13371337;
|
|
tb_cpu_instr = 1'h1;
|
|
tb_cpu_valid = 1'h1;
|
|
#(2 * CLK_PERIOD);
|
|
$display("--- test9: cpu_addr: 0x%08x, cpu_instr: 0x%1x, cpu_valid: 0x%1x",
|
|
tb_cpu_addr, tb_cpu_instr, tb_cpu_valid);
|
|
$display("--- test9: force_trap: 0x%1x", tb_force_trap);
|
|
|
|
$display("--- test9: completed.");
|
|
$display("");
|
|
end
|
|
endtask // test8
|
|
|
|
|
|
//----------------------------------------------------------------
|
|
// tk1_test
|
|
//----------------------------------------------------------------
|
|
initial
|
|
begin : tk1_test
|
|
$display("");
|
|
$display(" -= Testbench for tk1 started =-");
|
|
$display(" ===========================");
|
|
$display("");
|
|
|
|
init_sim();
|
|
reset_dut();
|
|
|
|
test1();
|
|
test2();
|
|
test3();
|
|
test4();
|
|
test5();
|
|
test6();
|
|
test7();
|
|
test8();
|
|
test9();
|
|
|
|
display_test_result();
|
|
$display("");
|
|
$display(" -= Testbench for tk1 completed =-");
|
|
$display(" =============================");
|
|
$display("");
|
|
$finish;
|
|
end // tk1_test
|
|
endmodule // tb_tk1
|
|
|
|
//======================================================================
|
|
// EOF tb_tk1.v
|
|
//======================================================================
|