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43 lines
1.2 KiB
Verilog
43 lines
1.2 KiB
Verilog
//======================================================================
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//
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// SB_RGBA_DRV.v
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// -------------
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// Dummy version of the SB_RGBA_DRV hard macro in Lattice iCE40 UP
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// devices. This is just to be able to build the testbench. The only
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// functionality we need is to be able to set the LEDs.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2023 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module SB_RGBA_DRV (
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output wire RGB0,
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output wire RGB1,
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output wire RGB2,
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input wire RGBLEDEN,
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input wire RGB0PWM,
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input wire RGB1PWM,
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input wire RGB2PWM,
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input wire CURREN
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);
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parameter CURRENT_MODE = 1;
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parameter RGB0_CURRENT = 8'h0;
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parameter RGB1_CURRENT = 8'h0;
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parameter RGB2_CURRENT = 8'h0;
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assign RGB0 = RGB0PWM;
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assign RGB1 = RGB1PWM;
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assign RGB2 = RGB2PWM;
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endmodule // SB_RGBA_DRV
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//======================================================================
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// EOF SB_RGBA_DRV.v
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//======================================================================
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