500 lines
13 KiB
Verilog
500 lines
13 KiB
Verilog
//======================================================================
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//
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// application_fpga.v
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// ------------------
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// Top level module of the application FPGA.
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// The design exposes a UART interface to allow a host to
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// send commands and receive resposes as needed load, execute and
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// communicate with applications.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2022 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module application_fpga(
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output wire interface_rx,
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input wire interface_tx,
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input wire touch_event,
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input wire app_gpio1,
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input wire app_gpio2,
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output wire app_gpio3,
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output wire app_gpio4,
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output wire led_r,
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output wire led_g,
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output wire led_b
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);
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//----------------------------------------------------------------
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// Local parameters
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//----------------------------------------------------------------
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// Top level mem area prefixes.
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localparam ROM_PREFIX = 2'h0;
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localparam RAM_PREFIX = 2'h1;
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localparam RESERVED_PREFIX = 2'h2;
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localparam MMIO_PREFIX = 2'h3;
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// MMIO core sub-prefixes.
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localparam TRNG_PREFIX = 6'h00;
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localparam TIMER_PREFIX = 6'h01;
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localparam UDS_PREFIX = 6'h02;
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localparam UART_PREFIX = 6'h03;
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localparam TOUCH_SENSE_PREFIX = 6'h04;
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localparam FW_RAM_PREFIX = 6'h10;
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localparam TK1_PREFIX = 6'h3f;
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// Instruction used to cause a trap.
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localparam ILLEGAL_INSTRUCTION = 32'h0;
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//----------------------------------------------------------------
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// Registers, memories with associated wires.
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//----------------------------------------------------------------
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reg [31 : 0] muxed_rdata_reg;
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reg [31 : 0] muxed_rdata_new;
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reg muxed_ready_reg;
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reg muxed_ready_new;
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//----------------------------------------------------------------
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// Wires.
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//----------------------------------------------------------------
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wire clk;
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wire reset_n;
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/* verilator lint_off UNOPTFLAT */
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wire cpu_trap;
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wire cpu_valid;
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wire cpu_instr;
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wire [03 : 0] cpu_wstrb;
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/* verilator lint_off UNUSED */
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wire [31 : 0] cpu_addr;
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wire [31 : 0] cpu_wdata;
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reg rom_cs;
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reg [11 : 0] rom_address;
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wire [31 : 0] rom_read_data;
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wire rom_ready;
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reg ram_cs;
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reg [3 : 0] ram_we;
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reg [14 : 0] ram_address;
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reg [31 : 0] ram_write_data;
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wire [31 : 0] ram_read_data;
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wire ram_ready;
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reg trng_cs;
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reg trng_we;
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reg [7 : 0] trng_address;
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reg [31 : 0] trng_write_data;
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wire [31 : 0] trng_read_data;
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wire trng_ready;
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reg timer_cs;
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reg timer_we;
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reg [7 : 0] timer_address;
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reg [31 : 0] timer_write_data;
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wire [31 : 0] timer_read_data;
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wire timer_ready;
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reg uds_cs;
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reg [2 : 0] uds_address;
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wire [31 : 0] uds_read_data;
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wire uds_ready;
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reg uart_cs;
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reg uart_we;
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reg [7 : 0] uart_address;
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reg [31 : 0] uart_write_data;
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wire [31 : 0] uart_read_data;
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wire uart_ready;
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reg fw_ram_cs;
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reg [3 : 0] fw_ram_we;
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reg [8 : 0] fw_ram_address;
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reg [31 : 0] fw_ram_write_data;
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wire [31 : 0] fw_ram_read_data;
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wire fw_ram_ready;
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reg touch_sense_cs;
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reg touch_sense_we;
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reg [7 : 0] touch_sense_address;
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wire [31 : 0] touch_sense_read_data;
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wire touch_sense_ready;
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reg tk1_cs;
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reg tk1_we;
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reg [7 : 0] tk1_address;
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reg [31 : 0] tk1_write_data;
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wire [31 : 0] tk1_read_data;
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wire tk1_ready;
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wire fw_app_mode;
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wire force_trap;
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wire [14 : 0] ram_aslr;
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wire [31 : 0] ram_scramble;
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/* verilator lint_on UNOPTFLAT */
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//----------------------------------------------------------------
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// Module instantiations.
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//----------------------------------------------------------------
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clk_reset_gen #(.RESET_CYCLES(200))
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reset_gen_inst(.clk(clk), .rst_n(reset_n));
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picorv32 #(
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.ENABLE_COUNTERS(0),
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.TWO_STAGE_SHIFT(0),
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.CATCH_MISALIGN(0),
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.COMPRESSED_ISA(1),
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.ENABLE_FAST_MUL(1),
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.BARREL_SHIFTER(1)
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) cpu(
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.clk(clk),
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.resetn(reset_n),
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.trap(cpu_trap),
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.mem_valid(cpu_valid),
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.mem_ready(muxed_ready_reg),
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.mem_addr (cpu_addr),
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.mem_wdata(cpu_wdata),
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.mem_wstrb(cpu_wstrb),
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.mem_rdata(muxed_rdata_reg),
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// Defined unused ports. Makes lint happy. But
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// we still needs to help lint with empty ports.
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/* verilator lint_off PINCONNECTEMPTY */
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.irq(32'h0),
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.eoi(),
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.trace_valid(),
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.trace_data(),
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.mem_instr(cpu_instr),
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.mem_la_read(),
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.mem_la_write(),
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.mem_la_addr(),
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.mem_la_wdata(),
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.mem_la_wstrb(),
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.pcpi_valid(),
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.pcpi_insn(),
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.pcpi_rs1(),
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.pcpi_rs2(),
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.pcpi_wr(1'h0),
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.pcpi_rd(32'h0),
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.pcpi_wait(1'h0),
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.pcpi_ready(1'h0)
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/* verilator lint_on PINCONNECTEMPTY */
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);
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rom rom_inst(
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.clk(clk),
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.reset_n(reset_n),
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.cs(rom_cs),
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.address(rom_address),
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.read_data(rom_read_data),
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.ready(rom_ready)
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);
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ram ram_inst(
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.clk(clk),
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.reset_n(reset_n),
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.cs(ram_cs),
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.we(ram_we),
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.address(ram_address),
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.write_data(ram_write_data),
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.read_data(ram_read_data),
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.ready(ram_ready)
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);
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fw_ram fw_ram_inst(
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.clk(clk),
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.reset_n(reset_n),
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.fw_app_mode(fw_app_mode),
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.cs(fw_ram_cs),
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.we(fw_ram_we),
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.address(fw_ram_address),
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.write_data(fw_ram_write_data),
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.read_data(fw_ram_read_data),
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.ready(fw_ram_ready)
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);
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rosc trng_inst(
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.clk(clk),
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.reset_n(reset_n),
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.cs(trng_cs),
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.we(trng_we),
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.address(trng_address),
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.write_data(trng_write_data),
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.read_data(trng_read_data),
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.ready(trng_ready)
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);
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timer timer_inst(
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.clk(clk),
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.reset_n(reset_n),
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.cs(timer_cs),
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.we(timer_we),
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.address(timer_address),
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.write_data(timer_write_data),
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.read_data(timer_read_data),
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.ready(timer_ready)
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);
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uds uds_inst(
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.clk(clk),
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.reset_n(reset_n),
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.fw_app_mode(fw_app_mode),
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.cs(uds_cs),
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.address(uds_address),
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.read_data(uds_read_data),
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.ready(uds_ready)
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);
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uart uart_inst(
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.clk(clk),
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.reset_n(reset_n),
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.rxd(interface_tx),
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.txd(interface_rx),
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.cs(uart_cs),
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.we(uart_we),
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.address(uart_address),
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.write_data(uart_write_data),
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.read_data(uart_read_data),
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.ready(uart_ready)
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);
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touch_sense touch_sense_inst(
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.clk(clk),
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.reset_n(reset_n),
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.touch_event(touch_event),
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.cs(touch_sense_cs),
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.we(touch_sense_we),
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.address(touch_sense_address),
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.read_data(touch_sense_read_data),
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.ready(touch_sense_ready)
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);
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tk1 tk1_inst(
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.clk(clk),
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.reset_n(reset_n),
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.fw_app_mode(fw_app_mode),
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.cpu_addr(cpu_addr),
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.cpu_instr(cpu_instr),
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.cpu_valid(cpu_valid),
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.cpu_trap(cpu_trap),
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.force_trap(force_trap),
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.ram_aslr(ram_aslr),
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.ram_scramble(ram_scramble),
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.led_r(led_r),
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.led_g(led_g),
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.led_b(led_b),
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.gpio1(app_gpio1),
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.gpio2(app_gpio2),
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.gpio3(app_gpio3),
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.gpio4(app_gpio4),
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.cs(tk1_cs),
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.we(tk1_we),
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.address(tk1_address),
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.write_data(tk1_write_data),
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.read_data(tk1_read_data),
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.ready(tk1_ready)
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);
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//----------------------------------------------------------------
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// Reg_update.
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// Posedge triggered with synchronous, active low reset.
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//----------------------------------------------------------------
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always @(posedge clk)
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begin : reg_update
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if (!reset_n) begin
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muxed_rdata_reg <= 32'h0;
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muxed_ready_reg <= 1'h0;
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end
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else begin
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muxed_rdata_reg <= muxed_rdata_new;
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muxed_ready_reg <= muxed_ready_new;
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end
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end
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//----------------------------------------------------------------
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// cpu_mem_ctrl
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// CPU memory decode and control logic.
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//----------------------------------------------------------------
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always @*
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begin : cpu_mem_ctrl
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reg [1 : 0] area_prefix;
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reg [5 : 0] core_prefix;
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area_prefix = cpu_addr[31 : 30];
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core_prefix = cpu_addr[29 : 24];
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muxed_ready_new = 1'h0;
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muxed_rdata_new = 32'h0;
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rom_cs = 1'h0;
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rom_address = cpu_addr[13 : 2];
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ram_cs = 1'h0;
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ram_we = 4'h0;
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ram_address = cpu_addr[16 : 2] ^ ram_aslr;
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ram_write_data = cpu_wdata ^ ram_scramble ^ {2{cpu_addr[15 : 0]}};
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fw_ram_cs = 1'h0;
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fw_ram_we = cpu_wstrb;
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fw_ram_address = cpu_addr[10 : 2];
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fw_ram_write_data = cpu_wdata;
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trng_cs = 1'h0;
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trng_we = |cpu_wstrb;
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trng_address = cpu_addr[9 : 2];
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trng_write_data = cpu_wdata;
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timer_cs = 1'h0;
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timer_we = |cpu_wstrb;
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timer_address = cpu_addr[9 : 2];
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timer_write_data = cpu_wdata;
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uds_cs = 1'h0;
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uds_address = cpu_addr[4 : 2];
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uart_cs = 1'h0;
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uart_we = |cpu_wstrb;
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uart_address = cpu_addr[9 : 2];
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uart_write_data = cpu_wdata;
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touch_sense_cs = 1'h0;
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touch_sense_we = |cpu_wstrb;
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touch_sense_address = cpu_addr[9 : 2];
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tk1_cs = 1'h0;
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tk1_we = |cpu_wstrb;
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tk1_address = cpu_addr[9 : 2];
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tk1_write_data = cpu_wdata;
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if (cpu_valid && !muxed_ready_reg) begin
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if (force_trap) begin
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muxed_rdata_new = ILLEGAL_INSTRUCTION;
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muxed_ready_new = 1'h1;
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end
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else begin
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case (area_prefix)
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ROM_PREFIX: begin
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rom_cs = 1'h1;
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muxed_rdata_new = rom_read_data;
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muxed_ready_new = rom_ready;
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end
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RAM_PREFIX: begin
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ram_cs = 1'h1;
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ram_we = cpu_wstrb;
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muxed_rdata_new = ram_read_data ^ ram_scramble ^ {2{cpu_addr[15 : 0]}};
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muxed_ready_new = ram_ready;
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end
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RESERVED_PREFIX: begin
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muxed_rdata_new = 32'h0;
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muxed_ready_new = 1'h1;
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end
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MMIO_PREFIX: begin
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case (core_prefix)
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TRNG_PREFIX: begin
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trng_cs = 1'h1;
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muxed_rdata_new = trng_read_data;
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muxed_ready_new = trng_ready;
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end
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TIMER_PREFIX: begin
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timer_cs = 1'h1;
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muxed_rdata_new = timer_read_data;
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muxed_ready_new = timer_ready;
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end
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UDS_PREFIX: begin
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uds_cs = 1'h1;
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muxed_rdata_new = uds_read_data;
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muxed_ready_new = uds_ready;
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end
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UART_PREFIX: begin
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uart_cs = 1'h1;
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muxed_rdata_new = uart_read_data;
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muxed_ready_new = uart_ready;
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end
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TOUCH_SENSE_PREFIX: begin
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touch_sense_cs = 1'h1;
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muxed_rdata_new = touch_sense_read_data;
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muxed_ready_new = touch_sense_ready;
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end
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FW_RAM_PREFIX: begin
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fw_ram_cs = 1'h1;
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muxed_rdata_new = fw_ram_read_data;
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muxed_ready_new = fw_ram_ready;
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end
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TK1_PREFIX: begin
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tk1_cs = 1'h1;
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muxed_rdata_new = tk1_read_data;
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muxed_ready_new = tk1_ready;
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end
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default: begin
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muxed_rdata_new = 32'h0;
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muxed_ready_new = 1'h1;
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end
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endcase // case (core_prefix)
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end // case: MMIO_PREFIX
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default: begin
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muxed_rdata_new = 32'h0;
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muxed_ready_new = 1'h1;
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end
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endcase // case (area_prefix)
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end
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end
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end
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endmodule // application_fpga
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//======================================================================
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// EOF application_fpga.v
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//======================================================================
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