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https://github.com/tillitis/tillitis-key1.git
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5e15b40a86
A proof-of-concept of enabling PicoRV32 interrupts. Two interrupt
sources, which can be triggered by writes to memory addresses, are
added. The design has only been simulated, not run on hardware.
Synthesis:
Ice40 LC utilization is 93% (4934/5280) when built using tkey-builder:4
Simulation:
A `tb_application_fpga_irqpoc` target is added. Running `make
tb_application_fpga_irqpoc` creates `tb_application_fpga_sim.fst` which
can be inspected in GTKWave or Surfer.
Firmware:
A simple firmware is added in `fw/irqpoc`. It enables both interrupts
and triggers each interrupt once.
Custom PicoRV32 instructions are located in `custom_ops.S`. It is
imported from upstream PicoRV32 commit:
70f3c33ac8
117 lines
3.7 KiB
Verilog
117 lines
3.7 KiB
Verilog
//======================================================================
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//
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// tb_application_fpga_sim.v
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// -------------------------
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// Top level module of the application_fpga.
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// The design exposes a UART interface to allow a host to
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// send commands and receive responses as needed load, execute and
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// communicate with applications.
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//
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//
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// Copyright (C) 2022 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`timescale 1ns / 1ns
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module tb_application_fpga_sim ();
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//----------------------------------------------------------------
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// Internal constant and parameter definitions.
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//----------------------------------------------------------------
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parameter CLK_HALF_PERIOD = 1;
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parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
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//----------------------------------------------------------------
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// Register and Wire declarations.
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//----------------------------------------------------------------
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reg tb_clk = 0;
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wire tb_interface_rx;
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reg tb_interface_tx = 1'h1; // Set to 1 to simulate inactive UART
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reg tb_interface_ch552_cts = 1'h1; // Set to 1 to simulate OK to send
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reg tb_interface_fpga_cts;
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wire tb_spi_ss;
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wire tb_spi_sck;
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wire tb_spi_mosi;
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reg tb_spi_miso;
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reg tb_touch_event;
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reg tb_app_gpio1;
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reg tb_app_gpio2;
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wire tb_app_gpio3;
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wire tb_app_gpio4;
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wire tb_led_r;
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wire tb_led_g;
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wire tb_led_b;
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//----------------------------------------------------------------
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// Device Under Test.
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//----------------------------------------------------------------
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application_fpga_sim dut (
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.clk(tb_clk),
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.interface_rx(tb_interface_rx),
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.interface_tx(tb_interface_tx),
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.interface_ch552_cts(tb_interface_ch552_cts),
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.interface_fpga_cts(tb_interface_fpga_cts),
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.spi_ss(tb_spi_ss),
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.spi_sck(tb_spi_sck),
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.spi_mosi(tb_spi_mosi),
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.spi_miso(tb_spi_miso),
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.touch_event(tb_touch_event),
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.app_gpio1(tb_app_gpio1),
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.app_gpio2(tb_app_gpio2),
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.app_gpio3(tb_app_gpio3),
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.app_gpio4(tb_app_gpio4),
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.led_r(tb_led_r),
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.led_g(tb_led_g),
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.led_b(tb_led_b)
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);
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//----------------------------------------------------------------
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// clk_gen
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//
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// Always running clock generator process.
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//----------------------------------------------------------------
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always begin : clk_gen
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#CLK_HALF_PERIOD;
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tb_clk = !tb_clk;
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end // clk_gen
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//----------------------------------------------------------------
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// finish
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//
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// End simulation
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//----------------------------------------------------------------
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initial begin
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// End simulation after XXX time units (set by timescale)
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#700;
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$display("TIMEOUT");
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$finish;
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end
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//----------------------------------------------------------------
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// Fill memories with data
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//----------------------------------------------------------------
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initial begin
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$readmemh("tb/output_spram0.hex", dut.ram_inst.spram0.mem);
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$readmemh("tb/output_spram1.hex", dut.ram_inst.spram1.mem);
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$readmemh("tb/output_spram2.hex", dut.ram_inst.spram2.mem);
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$readmemh("tb/output_spram3.hex", dut.ram_inst.spram3.mem);
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end
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//----------------------------------------------------------------
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// dumpfile
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//
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// Save waveform file
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//----------------------------------------------------------------
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initial begin
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$dumpfile("tb_application_fpga_sim.fst");
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$dumpvars(0, tb_application_fpga_sim);
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end
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endmodule // tb_application_fpga_sim
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//======================================================================
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// EOF tb_application_fpga_sim.v
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//======================================================================
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