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c35e7680ea
Silence lint on intentional combinatinal loops
Use better instance names, and a single lint pragma for all macros
Remove unused pointer update signals
Silence lint on wires where not all bits are used
Change fw_app_mode to be an input port to allow access control
Remove redundant, unused wire mem_busy
Add lint pragma to ignore debug register only enabled by a define
Remove clk and reset_n ports from the ROM
Adding note and lint pragma for rom address width
Fix incorrect register widths in uart_core
Assign all 16 bits in LUT config
Silence lint warnings on macro instances
Correct bit extraction for core addresses to be eight bits wide
Correct the bit width of cdi_mem_we wire
Add specific output file for logging lint issues
Correct bit width of tmp_ready to match one bit ready port
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trng
Implementation of the FiGaRO TRNG for FPGAs
Introduction
figaro
Status
First version completed. In testing. Use with caution.
Introduction
This is a an implementation of the FiGaRO true random number generator (TRNG) [1]. The main FPGA target is Lattice iCE40 UltraPlus, but adaption to other FPGAs should be easy to do.
Implementation details
The implementation instantiates four FiRO and four GaRO modules. The modules includes state sampling. The polynomials used for the oscillators are given by equotions (9)..(16) in paper [1]. The eight outputs are then XORed together to form a one bit random value.
The random bit value is sampled at a rate controlled by a 24 bit divisor.
References
[1] True Random Number Generator Based on Fibonacci-Galois Ring Oscillators for FPGA