tillitis-key/hw/application_fpga/application_fpga.bin.sha256 at c735c6fddec38644d15887ded833959c5448c2d0 - Git-Mirrors/tillitis-key - Gitea: Git with a cup of tea

Git-Mirrors/tillitis-key

mirror of https://github.com/tillitis/tillitis-key1.git synced 2025-07-04 02:46:49 -04:00

Daniel Jobson 6bdedf4f86

Fix bug in timer core, where it misses clock cycles

Remove redundant timer state. This fixes a bug where the timer misses a
clock cycle every time the prescaler counter reaches 1. This means if
one uses a large prescaler, like 18E6, it is barely noticeable, but if
one have a low prescaler and a high timer value it becomes significant.
This also yields the running_* registers redundant, which are removed.

Add clarity to the readme.

Update the timer to default to values of one, for prescaler and timer
count.

2024-11-27 08:10:15 +01:00

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2a3928e8587c8d5d7eca6048c6448dc1d16d52a9a25d3ca5026bec3e7fb14ef3 application_fpga.bin