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History

Jonas Thörnblad 3514d7ef3c FPGA: Format verilog code		2024-10-22 12:04:19 +02:00
..
rtl	FPGA: Format verilog code	2024-10-22 12:04:19 +02:00
tb	FPGA: Format verilog code	2024-10-22 12:04:19 +02:00
toolruns	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00
LICENSE	Make initial public release	2022-09-19 08:51:11 +02:00
README.md	Update the UART README with info about the core and its API	2023-07-04 09:04:25 +02:00

README.md

uart

A simple universal asynchronous receiver/transmitter (UART) core implemented in Verilog. The core is completed and has been used in several FPGA designs.

Introduction

The UART core is used as main communication channel between the TKey device System on Chip (SoC) and the TKey client. The UART contains a 512 byte receive buffer, allowing the SW running on the SoC to not have to wait for bytes and poll them as soon as they are received. The number of bytes in the FIFO is also exposed to the SW through the ADDR_RX_BYTES address.

The number of data and data bits can be set by SW. The default is eight data bits and one stop bit.

The default bit rate is based on target clock frequency divided by the bit rate times in order to hit the center of the bits. I.e. Clock: 18 MHz, 62500 bps Divisor = 18E6 / 62500 = 288

API

  ADDR_BIT_RATE:  0x10
  ADDR_DATA_BITS: 0x11
  ADDR_STOP_BITS: 0x12

  ADDR_RX_STATUS: 0x20
  ADDR_RX_DATA:   0x21
  ADDR_RX_BYTES:  0x22

  ADDR_TX_STATUS: 0x40
  ADDR_TX_DATA:   0x41

Implementation notes.

The FIFO allocates a single block RAM (EBR).