mirror of
https://github.com/tillitis/tillitis-key1.git
synced 2025-03-12 18:16:55 -04:00
bfc43093ec
Fix off-by-one UART bitrate counter value that will make the RX sampling and TX sending drift. The impact gets higher as the baudrate increases and the bitrate counter value gets smaller.
536 lines
16 KiB
Makefile
536 lines
16 KiB
Makefile
#=======================================================================
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#
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# Makefile
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# --------
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# Makefile for building, simulating, running all application_fpga
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# HW targets as well as its firmware.
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#
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#
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# Copyright (C) 2022-2024 - Tillitis AB
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# SPDX-License-Identifier: GPL-2.0-only
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#
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#
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# Please note: When creating a new cores and adding more testbenches,
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# please update the tb target below to include it as well.
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#
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#=======================================================================
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#-------------------------------------------------------------------
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# Defines.
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#-------------------------------------------------------------------
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SHELL := /bin/bash
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CUR_DIR := $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))
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P := $(CUR_DIR)
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YOSYS_PATH ?=
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NEXTPNR_PATH ?=
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ICESTORM_PATH ?=
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# FPGA target frequency. Should be in sync with the clock frequency
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# given by the parameters to the PLL in rtl/clk_reset_gen.v
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TARGET_FREQ ?= 24
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# Size in 32-bit words, must be divisible by 256 (pairs of EBRs, because 16
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# bits wide; an EBR is 128 32-bits words)
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BRAM_FW_SIZE ?= 1536
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PIN_FILE ?= application_fpga_tk1.pcf
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SIZE ?= llvm-size
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OBJCOPY ?= llvm-objcopy
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CC = clang
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CFLAGS = \
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-target riscv32-unknown-none-elf \
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-march=rv32iczmmul \
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-mabi=ilp32 \
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-static \
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-std=gnu99 \
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-O2 \
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-ffast-math \
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-fno-common \
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-fno-builtin-printf \
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-fno-builtin-putchar \
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-fno-builtin-memcpy \
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-nostdlib \
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-mno-relax \
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-Wall \
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-Wpedantic \
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-Wno-language-extension-token \
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-flto \
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-g
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AS = clang
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ASFLAGS = \
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-target riscv32-unknown-none-elf \
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-march=rv32iczmmul \
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-mabi=ilp32 \
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-mno-relax
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ICE40_SIM_CELLS = $(shell yosys-config --datdir/ice40/cells_sim.v)
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# FPGA specific source files.
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FPGA_VERILOG_SRCS = \
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$(P)/rtl/application_fpga.v \
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$(P)/core/clk_reset_gen/rtl/clk_reset_gen.v \
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$(P)/core/trng/rtl/trng.v
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# Testbench simulation specific source files.
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SIM_VERILOG_SRCS = \
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$(P)/tb/tb_application_fpga_sim.v \
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$(P)/tb/application_fpga_sim.v \
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$(P)/tb/reset_gen_sim.v \
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$(P)/tb/trng_sim.v
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# Verilator simulation specific source files.
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VERILATOR_VERILOG_SRCS = \
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$(P)/tb/application_fpga_sim.v \
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$(P)/tb/reset_gen_sim.v \
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$(P)/tb/trng_sim.v
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# Common verilog source files.
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VERILOG_SRCS = \
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$(P)/core/ram/rtl/ram.v \
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$(P)/core/rom/rtl/rom.v \
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$(P)/core/fw_ram/rtl/fw_ram.v \
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$(P)/core/timer/rtl/timer_core.v \
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$(P)/core/timer/rtl/timer.v \
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$(P)/core/uds/rtl/uds.v \
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$(P)/core/uds/rtl/uds_rom.v \
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$(P)/core/touch_sense/rtl/touch_sense.v \
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$(P)/core/tk1/rtl/tk1.v \
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$(P)/core/tk1/rtl/tk1_spi_master.v \
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$(P)/core/tk1/rtl/udi_rom.v \
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$(P)/core/uart/rtl/uart_core.v \
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$(P)/core/uart/rtl/uart_fifo.v \
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$(P)/core/uart/rtl/uart.v
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# PicoRV32 verilog source file
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PICORV32_SRCS = \
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$(P)/core/picorv32/rtl/picorv32.v
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FIRMWARE_DEPS = \
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$(P)/fw/tk1_mem.h \
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$(P)/fw/tk1/types.h \
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$(P)/fw/tk1/lib.h \
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$(P)/fw/tk1/proto.h \
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$(P)/fw/tk1/assert.h \
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$(P)/fw/tk1/led.h
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FIRMWARE_OBJS = \
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$(P)/fw/tk1/main.o \
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$(P)/fw/tk1/start.o \
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$(P)/fw/tk1/proto.o \
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$(P)/fw/tk1/lib.o \
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$(P)/fw/tk1/assert.o \
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$(P)/fw/tk1/led.o \
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$(P)/fw/tk1/blake2s/blake2s.o
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FIRMWARE_SOURCES = \
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$(P)/fw/tk1/main.c \
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$(P)/fw/tk1/proto.c \
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$(P)/fw/tk1/lib.c \
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$(P)/fw/tk1/assert.c \
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$(P)/fw/tk1/led.c \
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$(P)/fw/tk1/blake2s/blake2s.c
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TESTFW_OBJS = \
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$(P)/fw/testfw/main.o \
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$(P)/fw/testfw/start.o \
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$(P)/fw/tk1/proto.o \
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$(P)/fw/tk1/lib.o \
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$(P)/fw/tk1/blake2s/blake2s.o
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#-------------------------------------------------------------------
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# All: Complete build of HW and FW.
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#-------------------------------------------------------------------
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all: application_fpga.bin
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.PHONY: all
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#-------------------------------------------------------------------
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# The size_mismatch target make sure that we don't end up with an
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# incorrect BRAM_FW_SIZE
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# -------------------------------------------------------------------
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%_size_mismatch: %.elf phony_explicit
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@test $$($(SIZE) $< | awk 'NR==2{print $$4}') -le $$(( 32 / 8 * $(BRAM_FW_SIZE) )) \
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|| { printf "The 'BRAM_FW_SIZE' variable needs to be increased\n"; \
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[[ $< =~ testfw ]] && printf "Note that testfw fits if built with -Os\n"; \
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false; }
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# can't make implicit rule .PHONY
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phony_explicit:
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.PHONY: phony_explicit
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#-------------------------------------------------------------------
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# Personalization of the TKey
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#-------------------------------------------------------------------
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secret:
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cd data;../tools/tpt/tpt.py
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.PHONY: secret
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#-------------------------------------------------------------------
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# Firmware generation.
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# Included in the bitstream.
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#-------------------------------------------------------------------
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LDFLAGS = -T $(P)/fw/tk1/firmware.lds
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$(FIRMWARE_OBJS): $(FIRMWARE_DEPS)
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$(TESTFW_OBJS): $(FIRMWARE_DEPS)
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firmware.elf: $(FIRMWARE_OBJS) $(P)/fw/tk1/firmware.lds
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$(CC) $(CFLAGS) $(FIRMWARE_OBJS) $(LDFLAGS) -o $@
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simfirmware.elf: CFLAGS += -DSIMULATION
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simfirmware.elf: $(FIRMWARE_OBJS) $(P)/fw/tk1/firmware.lds
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$(CC) $(CFLAGS) $(FIRMWARE_OBJS) $(LDFLAGS) -o $@
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qemu_firmware.elf: CFLAGS += -DQEMU_CONSOLE
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qemu_firmware.elf: firmware.elf
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mv firmware.elf qemu_firmware.elf
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# Create compile_commands.json for clangd and LSP
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.PHONY: clangd
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clangd: compile_commands.json
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compile_commands.json:
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$(MAKE) clean
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bear -- make qemu_firmware.elf
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.PHONY: check
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check:
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clang-tidy -header-filter=.* -checks=cert-* $(FIRMWARE_SOURCES) -- $(CFLAGS)
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.PHONY: splint
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splint:
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splint \
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-nolib \
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-predboolint \
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+boolint \
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-nullpass \
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-unrecog \
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-infloops \
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-initallelements \
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-type \
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-unreachable \
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-unqualifiedtrans \
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-fullinitblock \
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$(FIRMWARE_SOURCES)
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testfw.elf: $(TESTFW_OBJS) $(P)/fw/tk1/firmware.lds
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$(CC) $(CFLAGS) $(TESTFW_OBJS) $(LDFLAGS) -o $@
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# Generate a fake BRAM file that will be filled in later after place-n-route
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bram_fw.hex:
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$(ICESTORM_PATH)icebram -v -g 32 $(BRAM_FW_SIZE) > $@
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firmware.hex: firmware.bin firmware_size_mismatch
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python3 $(P)/tools/makehex/makehex.py $< $(BRAM_FW_SIZE) > $@
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simfirmware.hex: simfirmware.bin simfirmware_size_mismatch
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python3 $(P)/tools/makehex/makehex.py $< $(BRAM_FW_SIZE) > $@
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testfw.hex: testfw.bin testfw_size_mismatch
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python3 $(P)/tools/makehex/makehex.py $< $(BRAM_FW_SIZE) > $@
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.PHONY: check-binary-hashes
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check-binary-hashes:
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sha512sum firmware.bin
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sha256sum application_fpga.bin
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sha512sum -c firmware.bin.sha512
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sha256sum -c application_fpga.bin.sha256
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%.bin: %.elf
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$(SIZE) $<
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@test "$$($(SIZE) $< | awk 'NR==2{print $$2, $$3}')" = "0 0" \
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|| { printf "Non-empty data or bss section!\n"; false; }
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$(OBJCOPY) --input-target=elf32-littleriscv --output-target=binary $< $@
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chmod -x $@
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#-------------------------------------------------------------------
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# Source linting.
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#-------------------------------------------------------------------
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LINT = verilator
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# For Verilator 5.019 -Wno-GENUNNAMED needs to be added to LINT_FLAGS for the
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# cell library.
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LINT_FLAGS = \
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+1364-2005ext+ \
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--lint-only \
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-Wall \
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-Wno-DECLFILENAME \
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-Wno-WIDTHEXPAND \
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-Wno-UNOPTFLAT \
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--timescale 1ns/1ns \
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-DNO_ICE40_DEFAULT_ASSIGNMENTS
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lint: $(FPGA_VERILOG_SRCS) \
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$(SIM_VERILOG_SRCS) \
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$(VERILOG_SRCS) \
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$(PICORV32_SRCS) \
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$(ICE40_SIM_CELLS)
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$(LINT) $(LINT_FLAGS) \
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-DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \
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-DFIRMWARE_HEX=\"$(P)/firmware.hex\" \
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-DUDS_HEX=\"$(P)/data/uds.hex\" \
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-DUDI_HEX=\"$(P)/data/udi.hex\" \
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--top-module application_fpga \
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config.vlt $^ \
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>lint_issues.txt 2>&1 \
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&& { rm -f lint_issues.txt; exit 0; } \
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|| { cat lint_issues.txt; exit 1; }
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.PHONY: lint
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#-------------------------------------------------------------------
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# Source formatting.
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#-------------------------------------------------------------------
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FORMAT = verible-verilog-format
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FORMAT_FLAGS = \
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--indentation_spaces=2 \
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--wrap_end_else_clauses=true \
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--inplace
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CHECK_FORMAT_FLAGS = \
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--indentation_spaces=2 \
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--wrap_end_else_clauses=true \
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--inplace \
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--verify
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fmt: $(FPGA_VERILOG_SRCS) $(SIM_VERILOG_SRCS) $(VERILATOR_VERILOG_SRCS) $(VERILOG_SRCS)
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$(FORMAT) $(FORMAT_FLAGS) $^
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.PHONY: fmt
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# Temporary fix using grep, since the verible with --verify flag only returns
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# error if the last file is malformatted.
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checkfmt: $(FPGA_VERILOG_SRCS) $(SIM_VERILOG_SRCS) $(VERILATOR_VERILOG_SRCS) $(VERILOG_SRCS)
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$(FORMAT) $(CHECK_FORMAT_FLAGS) $^ 2>&1 | \
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grep "Needs formatting" && exit 1 || true
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.PHONY: checkfmt
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#-------------------------------------------------------------------
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# Build Verilator compiled simulation for the design.
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#-------------------------------------------------------------------
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verilator: $(VERILATOR_VERILOG_SRCS) $(VERILOG_SRCS) $(PICORV32_SRCS) \
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firmware.hex $(ICE40_SIM_CELLS) \
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$(P)/tb/application_fpga_verilator.cc
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verilator \
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--timescale 1ns/1ns \
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-DNO_ICE40_DEFAULT_ASSIGNMENTS \
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-Wall \
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-Wno-COMBDLY \
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-Wno-lint \
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-Wno-UNOPTFLAT \
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-DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \
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-DFIRMWARE_HEX=\"$(P)/firmware.hex\" \
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-DUDS_HEX=\"$(P)/data/uds.hex\" \
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-DUDI_HEX=\"$(P)/data/udi.hex\" \
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--cc \
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--exe \
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--Mdir verilated \
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--top-module application_fpga_sim \
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$(filter %.v, $^) \
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$(filter %.cc, $^)
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make -C verilated -f Vapplication_fpga_sim.mk
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.PHONY: verilator
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#-------------------------------------------------------------------
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# Run all testbenches
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#-------------------------------------------------------------------
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tb:
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make -C core/timer/toolruns sim-top
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make -C core/tk1/toolruns sim-top
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make -C core/touch_sense/toolruns sim-top
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make -C core/trng/toolruns sim-top
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make -C core/uart/toolruns sim-top
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make -C core/uds/toolruns sim-top
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.PHONY: tb
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#-------------------------------------------------------------------
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# Main FPGA build flow.
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# Synthesis. Place & Route. Bitstream generation.
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#-------------------------------------------------------------------
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YOSYS_FLAG ?=
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synth.json: $(FPGA_VERILOG_SRCS) $(VERILOG_SRCS) $(PICORV32_SRCS) bram_fw.hex
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$(YOSYS_PATH)yosys \
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-v3 \
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-l synth.txt \
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$(YOSYS_FLAG) \
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-DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \
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-DFIRMWARE_HEX=\"$(P)/bram_fw.hex\" \
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-p 'synth_ice40 -abc2 -device u -dff -dsp -top application_fpga -json $@' \
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-p 'write_verilog -attr2comment synth.v' \
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$(filter %.v, $^)
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application_fpga_par.json: synth.json $(P)/data/$(PIN_FILE)
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$(NEXTPNR_PATH)nextpnr-ice40 \
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-l application_fpga_par.txt \
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--seed 9106179903728618585 \
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--freq $(TARGET_FREQ) \
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--ignore-loops \
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--up5k \
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--package sg48 \
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--json $< \
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--pcf $(P)/data/$(PIN_FILE) \
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--write $@ \
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&& { exit 0; } \
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|| { rm -f application_fpga_par.json; exit 1; }
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application_fpga.asc: application_fpga_par.json $(P)/data/uds.hex $(P)/data/udi.hex
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UDS_HEX="$(P)/data/uds.hex" \
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UDI_HEX="$(P)/data/udi.hex" \
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OUT_ASC=$@ \
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$(NEXTPNR_PATH)nextpnr-ice40 \
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--up5k \
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--package sg48 \
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--ignore-loops \
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--json $< \
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--run tools/patch_uds_udi.py
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application_fpga.bin: application_fpga.asc bram_fw.hex firmware.hex
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$(ICESTORM_PATH)icebram -v bram_fw.hex firmware.hex < $< > $<.tmp
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$(ICESTORM_PATH)icepack $<.tmp $@
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@-$(RM) $<.tmp
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application_fpga_testfw.bin: application_fpga.asc bram_fw.hex testfw.hex
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$(ICESTORM_PATH)icebram -v bram_fw.hex testfw.hex < $< > $<.tmp
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$(ICESTORM_PATH)icepack $<.tmp $@
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@-$(RM) $<.tmp
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#-------------------------------------------------------------------
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# Build testbench simulation for the design
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#-------------------------------------------------------------------
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tb_application_fpga: $(SIM_VERILOG_SRCS) \
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$(VERILOG_SRCS) \
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$(PICORV32_SRCS) \
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$(ICE40_SIM_CELLS) \
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simfirmware.hex
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python3 ./tools/app_bin_to_spram_hex.py \
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./tb/app.bin \
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./tb/output_spram0.hex \
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./tb/output_spram1.hex \
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./tb/output_spram2.hex \
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./tb/output_spram3.hex \
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|| { echo -e "\n -- Put your app.bin to simulate in the \"tb\" directory\n"; false; }
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verilator \
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-j $(shell nproc --ignore=1) \
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--binary \
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--cc \
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--exe \
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--Mdir tb_verilated \
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--trace-fst \
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--trace-structs \
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--top-module tb_application_fpga_sim \
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--timescale 1ns/1ns \
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--timing \
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-Wno-WIDTHEXPAND \
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-Wno-UNOPTFLAT \
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-DNO_ICE40_DEFAULT_ASSIGNMENTS \
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-DAPP_SIZE=$(shell ls -l tb/app.bin| awk '{print $$5}') \
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-DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \
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-DFIRMWARE_HEX=\"$(P)/simfirmware.hex\" \
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-DUDS_HEX=\"$(P)/data/uds.hex\" \
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-DUDI_HEX=\"$(P)/data/udi.hex\" \
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$(filter %.v, $^)
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make -C tb_verilated -f Vtb_application_fpga_sim.mk
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./tb_verilated/Vtb_application_fpga_sim \
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&& { echo -e "\n -- Wave simulation saved to tb_application_fpga_sim.fst\n"; true; }
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#-------------------------------------------------------------------
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# FPGA device programming.
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#-------------------------------------------------------------------
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prog_flash: check-hardware application_fpga.bin
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sudo tillitis-iceprog application_fpga.bin
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.PHONY: prog_flash
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prog_flash_testfw: check-hardware application_fpga_testfw.bin
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sudo tillitis-iceprog application_fpga_testfw.bin
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.PHONY: prog_flash_testfw
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check-hardware:
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@sudo tillitis-iceprog -t >/dev/null 2>&1 || \
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{ echo "Programmer not plugged in or not accessible"; false; }
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@if sudo tillitis-iceprog -t 2>&1 | grep -qi "^flash.id:\( 0x\(00\|ff\)\)\{4\}"; then \
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echo "No USB stick in the programmer?"; false; else true; fi
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.PHONY: check-hardware
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#-------------------------------------------------------------------
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# Post build analysis.
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#-------------------------------------------------------------------
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timing: application_fpga.asc $(P)/data/$(PIN_FILE)
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$(ICESTORM_PATH)icetime -c 18 -tmd up5k -P sg48 -p $(P)/data/$(PIN_FILE) -t $<
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view: tb_application_fpga_vcd
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gtkwave $< application_fpga.gtkw
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#-------------------------------------------------------------------
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# Cleanup.
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#-------------------------------------------------------------------
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clean: clean_sim clean_fw clean_tb
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rm -f bram_fw.hex
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rm -f synth.{v,json,txt} application_fpga.{asc,bin} application_fpga_testfw.bin
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rm -f application_fpga_par.{json,txt}
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|
rm -f lint_issues.txt
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|
rm -f tools/tpt/*.hex
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|
rm -rf tools/tpt/__pycache__
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|
.PHONY: clean
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|
|
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clean_fw:
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|
rm -f firmware.{elf,elf.map,bin,hex}
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rm -f $(FIRMWARE_OBJS)
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|
rm -f testfw.{elf,elf.map,bin,hex}
|
|
rm -f $(TESTFW_OBJS)
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|
rm -f qemu_firmware.elf
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|
.PHONY: clean_fw
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|
|
|
clean_sim:
|
|
rm -f simfirmware.{elf,elf.map,bin,hex}
|
|
rm -f tb_application_fpga_sim.fst
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|
rm -f tb_application_fpga_sim.fst.hier
|
|
rm -f tb/output_spram*.hex
|
|
rm -rf tb_verilated
|
|
rm -rf verilated
|
|
.PHONY: clean_sim
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|
|
|
clean_tb:
|
|
make -C core/timer/toolruns clean
|
|
make -C core/tk1/toolruns clean
|
|
make -C core/touch_sense/toolruns clean
|
|
make -C core/trng/toolruns clean
|
|
make -C core/uart/toolruns clean
|
|
make -C core/uds/toolruns clean
|
|
.PHONY: clean_tb
|
|
|
|
#-------------------------------------------------------------------
|
|
# Display info about targets.
|
|
#-------------------------------------------------------------------
|
|
help:
|
|
@echo ""
|
|
@echo "Build system for application_fpga FPGA design and firmware."
|
|
@echo ""
|
|
@echo "Supported targets:"
|
|
@echo "------------------"
|
|
@echo "all Build all targets."
|
|
@echo "check Run static analysis on firmware."
|
|
@echo "splint Run splint static analysis on firmware."
|
|
@echo "firmware.elf Build firmware ELF file."
|
|
@echo "firmware.hex Build firmware converted to hex, to be included in bitstream."
|
|
@echo "bram_fw.hex Build a fake BRAM file that will be filled in later after place-n-route."
|
|
@echo "verilator Build Verilator simulation program"
|
|
@echo "tb_application_fpga Build testbench simulation for the design"
|
|
@echo "lint Run lint on Verilog source files."
|
|
@echo "tb Run all testbenches"
|
|
@echo "prog_flash Program device flash with FGPA bitstream including firmware (using the RPi Pico-based programmer)."
|
|
@echo "prog_flash_testfw Program device flash as above, but with testfw."
|
|
@echo "clean Delete all generated files."
|
|
@echo "clean_fw Delete only generated files for firmware. Useful for fw devs."
|
|
@echo "clean_tb Delete only generated files for testbenches."
|
|
|
|
#=======================================================================
|
|
# EOF Makefile
|
|
#=======================================================================
|