mirror of
https://github.com/tillitis/tillitis-key1.git
synced 2024-10-01 01:45:38 -04:00
b1993742bb
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
321 lines
8.4 KiB
Verilog
321 lines
8.4 KiB
Verilog
//======================================================================
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//
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// tb_tk1.v
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// --------
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// Testbench for the TK1 core.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2023 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module tb_tk1();
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//----------------------------------------------------------------
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// Internal constant and parameter definitions.
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//----------------------------------------------------------------
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parameter DEBUG = 1;
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parameter CLK_HALF_PERIOD = 1;
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parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
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localparam ADDR_NAME0 = 8'h00;
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localparam ADDR_NAME1 = 8'h01;
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localparam ADDR_VERSION = 8'h02;
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localparam ADDR_SWITCH_APP = 8'h08;
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localparam ADDR_LED = 8'h09;
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localparam LED_R_BIT = 2;
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localparam LED_G_BIT = 1;
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localparam LED_B_BIT = 0;
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localparam ADDR_GPIO = 8'h0a;
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localparam GPIO1_BIT = 0;
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localparam GPIO2_BIT = 1;
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localparam GPIO3_BIT = 2;
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localparam GPIO4_BIT = 3;
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localparam ADDR_APP_START = 8'h0c;
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localparam ADDR_APP_SIZE = 8'h0d;
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localparam ADDR_BLAKE2S = 8'h10;
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localparam ADDR_CDI_FIRST = 8'h20;
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localparam ADDR_CDI_LAST = 8'h27;
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localparam ADDR_UDI_FIRST = 8'h30;
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localparam ADDR_UDI_LAST = 8'h31;
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localparam ADDR_RAM_ASLR = 8'h40;
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localparam ADDR_RAM_SCRAMBLE = 8'h41;
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localparam ADDR_CPU_MON_CTRL = 8'h60;
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localparam ADDR_CPU_MON_FIRST = 8'h61;
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localparam ADDR_CPU_MON_LAST = 8'h62;
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//----------------------------------------------------------------
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// Register and Wire declarations.
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//----------------------------------------------------------------
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reg [31 : 0] cycle_ctr;
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reg [31 : 0] error_ctr;
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reg [31 : 0] tc_ctr;
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reg tb_monitor;
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reg tb_clk;
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reg tb_reset_n;
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reg tb_cpu_trap;
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wire tb_fw_app_mode;
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reg [31 : 0] tb_cpu_addr;
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reg tb_cpu_instr;
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reg tb_cpu_valid;
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wire tb_force_trap;
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wire [14 : 0] tb_ram_aslr;
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wire [31 : 0] tb_ram_scramble;
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wire tb_led_r;
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wire tb_led_g;
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wire tb_led_b;
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reg tb_gpio1;
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reg tb_gpio2;
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wire tb_gpio3;
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wire tb_gpio4;
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reg tb_cs;
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reg tb_we;
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reg [7 : 0] tb_address;
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reg [31 : 0] tb_write_data;
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wire [31 : 0] tb_read_data;
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wire tb_ready;
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//----------------------------------------------------------------
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// Device Under Test.
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//----------------------------------------------------------------
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tk1 dut(
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.clk(tb_clk),
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.reset_n(tb_reset_n),
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.cpu_trap(tb_cpu_trap),
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.fw_app_mode(tb_fw_app_mode),
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.cpu_addr(tb_cpu_addr),
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.cpu_instr(tb_cpu_instr),
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.cpu_valid(tb_cpu_valid),
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.force_trap(tb_force_trap),
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.ram_aslr(tb_ram_aslr),
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.ram_scramble(tb_ram_scramble),
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.led_r(tb_led_r),
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.led_g(tb_led_g),
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.led_b(tb_led_b),
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.gpio1(tb_gpio1),
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.gpio2(tb_gpio2),
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.gpio3(tb_gpio3),
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.gpio4(tb_gpio4),
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.cs(tb_cs),
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.we(tb_we),
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.address(tb_address),
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.write_data(tb_write_data),
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.read_data(tb_read_data),
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.ready(tb_ready)
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);
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//----------------------------------------------------------------
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// clk_gen
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//
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// Always running clock generator process.
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//----------------------------------------------------------------
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always
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begin : clk_gen
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#CLK_HALF_PERIOD;
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tb_clk = !tb_clk;
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end // clk_gen
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//----------------------------------------------------------------
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// sys_monitor()
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//
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// An always running process that creates a cycle counter and
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// conditionally displays information about the DUT.
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//----------------------------------------------------------------
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always
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begin : sys_monitor
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cycle_ctr = cycle_ctr + 1;
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#(CLK_PERIOD);
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if (tb_monitor)
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begin
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dump_dut_state();
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end
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end
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//----------------------------------------------------------------
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// dump_dut_state()
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//
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// Dump the state of the dump when needed.
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//----------------------------------------------------------------
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task dump_dut_state;
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begin : dump_dut_state
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$display("State of DUT at cycle: %08d", cycle_ctr);
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$display("------------");
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$display("Inputs and outputs:");
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$display("fw_app_mode: 0x%1x", tb_fw_app_mode);
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$display("cs: 0x%1x, address: 0x%02x, read_data: 0x%08x", tb_cs, tb_address, tb_read_data);
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$display("");
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$display("Internal state:");
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$display("tmp_read_ready: 0x%1x, tmp_read_data: 0x%08x", dut.tmp_ready, dut.tmp_read_data);
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$display("");
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$display("");
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end
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endtask // dump_dut_state
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//----------------------------------------------------------------
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// reset_dut()
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//
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// Toggle reset to put the DUT into a well known state.
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//----------------------------------------------------------------
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task reset_dut;
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begin
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$display("--- Toggle reset.");
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tb_reset_n = 0;
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#(2 * CLK_PERIOD);
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tb_reset_n = 1;
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end
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endtask // reset_dut
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//----------------------------------------------------------------
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// display_test_result()
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//
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// Display the accumulated test results.
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//----------------------------------------------------------------
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task display_test_result;
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begin
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if (error_ctr == 0)
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begin
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$display("--- All %02d test cases completed successfully", tc_ctr);
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end
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else
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begin
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$display("--- %02d tests completed - %02d test cases did not complete successfully.",
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tc_ctr, error_ctr);
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end
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end
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endtask // display_test_result
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//----------------------------------------------------------------
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// init_sim()
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//
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// Initialize all counters and testbed functionality as well
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// as setting the DUT inputs to defined values.
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//----------------------------------------------------------------
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task init_sim;
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begin
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cycle_ctr = 0;
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error_ctr = 0;
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tc_ctr = 0;
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tb_monitor = 0;
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tb_clk = 1'h0;
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tb_reset_n = 1'h1;
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tb_cs = 1'h0;
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tb_address = 8'h0;
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end
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endtask // init_sim
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//----------------------------------------------------------------
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// read_word()
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//
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// Read a data word from the given address in the DUT.
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// the word read will be available in the global variable
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// read_data.
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//----------------------------------------------------------------
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task read_word(input [11 : 0] address, input [31 : 0] expected);
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begin : read_word
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reg [31 : 0] read_data;
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tb_address = address;
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tb_cs = 1'h1;
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#(CLK_HALF_PERIOD);
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read_data = tb_read_data;
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#(CLK_HALF_PERIOD);
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tb_cs = 1'h0;
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if (DEBUG)
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begin
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if (read_data == expected) begin
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$display("--- Reading 0x%08x from 0x%02x.", read_data, address);
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end else begin
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$display("--- Error: Got 0x%08x when reading from 0x%02x, expected 0x%08x",
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read_data, address, expected);
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error_ctr = error_ctr + 1;
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end
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$display("");
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end
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end
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endtask // read_word
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//----------------------------------------------------------------
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// test1()
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//----------------------------------------------------------------
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task test1;
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begin
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tc_ctr = tc_ctr + 1;
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$display("");
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$display("--- test1: started.");
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$display("--- test1: completed.");
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$display("");
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end
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endtask // test1
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//----------------------------------------------------------------
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// tk1_test
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//----------------------------------------------------------------
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initial
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begin : tk1_test
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$display("");
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$display(" -= Testbench for tk1 started =-");
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$display(" ===========================");
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$display("");
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init_sim();
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reset_dut();
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test1();
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display_test_result();
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$display("");
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$display(" -= Testbench for tk1 completed =-");
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$display(" =============================");
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$display("");
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$finish;
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end // tk1_test
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endmodule // tb_tk1
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//======================================================================
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// EOF tb_tk1.v
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//======================================================================
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