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tillitis-key/hw
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Jonas Thörnblad aaec7bbc3e
Add incoming and outgoing CTS (Clear To Send) signals for the FPGA 
to let the CH552 and FPGA signal each other that it is OK to send
UART data. The CTS signals indicate "OK to send" if high. If an
incoming CTS signal goes low, the receiver of that signal should
immediatly stop sending UART data.
2025-01-09 10:55:50 +01:00
..
application_fpga
Add incoming and outgoing CTS (Clear To Send) signals for the FPGA
2025-01-09 10:55:50 +01:00
usb_interface/ch552_fw
Wrap accesses to UART output buffers
2025-01-09 10:55:19 +01:00