mirror of
https://github.com/tillitis/tillitis-key1.git
synced 2024-10-01 01:45:38 -04:00
a76fc19c65
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
30 lines
678 B
Verilog
30 lines
678 B
Verilog
//======================================================================
|
|
//
|
|
// SB_LUT4.v
|
|
// ---------
|
|
// Simulation model of the SB_LUT4 macro used to buil the sim target.
|
|
//
|
|
//
|
|
// Author: Joachim Strombergson
|
|
// Copyright (C) 2023 - Tillitis AB
|
|
// SPDX-License-Identifier: GPL-2.0-only
|
|
//
|
|
//======================================================================
|
|
|
|
`default_nettype none
|
|
|
|
module SB_LUT4 (
|
|
input wire I0,
|
|
output wire O
|
|
);
|
|
|
|
parameter LUT_INIT = 16'h0;
|
|
|
|
assign O = ~I0;
|
|
|
|
endmodule // SB_LUT4
|
|
|
|
//======================================================================
|
|
// EOF SB_LUT4.v
|
|
//======================================================================
|