mirror of
https://github.com/tillitis/tillitis-key1.git
synced 2024-12-20 21:34:28 -05:00
305 lines
10 KiB
Makefile
305 lines
10 KiB
Makefile
#=======================================================================
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#
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# Makefile
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# --------
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# Makefile for building, simulating, running all application_fpga
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# HW targets as well as its firmware.
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#
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#
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# Copyright (C) 2022 - Tillitis AB
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# SPDX-License-Identifier: GPL-2.0-only
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#
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#=======================================================================
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#-------------------------------------------------------------------
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# Defines.
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#-------------------------------------------------------------------
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SHELL := /bin/bash
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CUR_DIR := $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))
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P := $(CUR_DIR)
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YOSYS_PATH ?=
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NEXTPNR_PATH ?=
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ICESTORM_PATH ?=
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# Size in 32-bit words, must be divisible by 256 (pairs of EBRs, because 16
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# bits wide; an EBR is 128 32-bits words)
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BRAM_FW_SIZE ?= 1536
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PIN_FILE ?= application_fpga_mta1_usb_v1.pcf
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SIZE ?= llvm-size
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OBJCOPY ?= llvm-objcopy
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CC = clang
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CFLAGS = -target riscv32-unknown-none-elf -march=rv32iczmmul -mabi=ilp32 \
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-static -std=gnu99 -Os -ffast-math -fno-common -fno-builtin-printf \
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-fno-builtin-putchar -nostdlib -mno-relax -Wall -flto -DNOCONSOLE
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AS = clang
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ASFLAGS = -target riscv32-unknown-none-elf -march=rv32iczmmul -mabi=ilp32 -mno-relax
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ICE40_SIM_CELLS = $(shell yosys-config --datdir/ice40/cells_sim.v)
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# FPGA specific source files.
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FPGA_SRC = $(P)/rtl/application_fpga.v \
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$(P)/rtl/clk_reset_gen.v
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# Verilator simulation specific source files.
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VERILATOR_FPGA_SRC = $(P)/tb/application_fpga_vsim.v \
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$(P)/tb/reset_gen_vsim.v
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# Common verilog source files.
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VERILOG_SRCS = \
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$(P)/rtl/ram.v \
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$(P)/rtl/rom.v \
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$(P)/rtl/fw_ram.v \
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$(P)/core/picorv32/rtl/picorv32.v \
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$(P)/core/timer/rtl/timer_core.v \
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$(P)/core/timer/rtl/timer.v \
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$(P)/core/uds/rtl/uds.v \
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$(P)/core/touch_sense/rtl/touch_sense.v \
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$(P)/core/tk1/rtl/tk1.v \
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$(P)/core/uart/rtl/uart_core.v \
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$(P)/core/uart/rtl/uart_fifo.v \
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$(P)/core/uart/rtl/uart.v \
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$(P)/core/trng/rtl/rosc.v
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FIRMWARE_DEPS = \
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$(P)/fw/tk1_mem.h \
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$(P)/fw/tk1/types.h \
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$(P)/fw/tk1/lib.h \
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$(P)/fw/tk1/proto.h
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FIRMWARE_OBJS = \
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$(P)/fw/tk1/main.o \
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$(P)/fw/tk1/start.o \
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$(P)/fw/tk1/proto.o \
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$(P)/fw/tk1/lib.o \
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$(P)/fw/tk1/blake2s/blake2s.o
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TESTFW_OBJS = \
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$(P)/fw/testfw/main.o \
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$(P)/fw/tk1/start.o \
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$(P)/fw/tk1/proto.o \
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$(P)/fw/tk1/lib.o
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#-------------------------------------------------------------------
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# All: Complete build of HW and FW.
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#-------------------------------------------------------------------
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all: application_fpga.bin
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.PHONY: all
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#-------------------------------------------------------------------
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# The size_mismatch target make sure that we don't end up with an
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# incorrect BRAM_FW_SIZE
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# -------------------------------------------------------------------
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%_size_mismatch: %.elf phony_explicit
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@test $$($(SIZE) $< | awk 'NR==2{print $$4}') -le $$(( 32 / 8 * $(BRAM_FW_SIZE) )) || \
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(echo "The 'BRAM_FW_SIZE' variable needs to be increased" && false)
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# can't make implicit rule .PHONY
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phony_explicit:
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.PHONY: phony_explicit
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#-------------------------------------------------------------------
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# Personalization of the TK1
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#-------------------------------------------------------------------
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secret:
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cd data;../tools/tpt/tpt.py
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.PHONY: secret
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#-------------------------------------------------------------------
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# Firmware generation.
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# Included in the bitstream.
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#-------------------------------------------------------------------
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LDFLAGS=-T $(P)/fw/tk1/firmware.lds
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$(FIRMWARE_OBJS): $(FIRMWARE_DEPS)
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$(TESTFW_OBJS): $(FIRMWARE_DEPS)
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firmware.elf: $(FIRMWARE_OBJS) $(P)/fw/tk1/firmware.lds
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$(CC) $(CFLAGS) $(FIRMWARE_OBJS) $(LDFLAGS) -o $@
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testfw.elf: $(TESTFW_OBJS) $(P)/fw/tk1/firmware.lds
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$(CC) $(CFLAGS) $(TESTFW_OBJS) $(LDFLAGS) -o $@
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# Generate a fake BRAM file that will be filled in later after place-n-route
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bram_fw.hex:
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$(ICESTORM_PATH)icebram -v -g 32 $(BRAM_FW_SIZE) > $@
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firmware.hex: firmware.bin firmware_size_mismatch
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python3 $(P)/tools/makehex/makehex.py $< $(BRAM_FW_SIZE) > $@
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testfw.hex: testfw.bin testfw_size_mismatch
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python3 $(P)/tools/makehex/makehex.py $< $(BRAM_FW_SIZE) > $@
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%.bin: %.elf
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$(SIZE) $<
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$(OBJCOPY) --input-target=elf32-littleriscv --output-target=binary $< $@
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chmod -x $@
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#-------------------------------------------------------------------
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# Source linting.
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#-------------------------------------------------------------------
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LINT=verilator
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LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME \
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--timescale 1ns/1ns -DNO_ICE40_DEFAULT_ASSIGNMENTS
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lint: $(FPGA_SRC) $(VERILOG_SRCS) $(ICE40_SIM_CELLS)
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$(LINT) $(LINT_FLAGS) \
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-DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \
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-DFIRMWARE_HEX=\"$(P)/firmware.hex\" \
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-DUDS_HEX=\"$(P)/data/uds.hex\" \
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-DUDI_HEX=\"$(P)/data/udi.hex\" \
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--top-module application_fpga $^ &> lint_issues.txt
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.PHONY: lint
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#-------------------------------------------------------------------
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# Build Verilator compiled simulation for the design.
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#-------------------------------------------------------------------
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verilator: $(VERILATOR_FPGA_SRC) $(VERILOG_SRCS) firmware.hex $(ICE40_SIM_CELLS) \
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$(P)/tb/application_fpga_verilator.cc
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verilator --timescale 1ns/1ns -DNO_ICE40_DEFAULT_ASSIGNMENTS \
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-Wall -Wno-COMBDLY -Wno-lint \
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-DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \
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-DFIRMWARE_HEX=\"$(P)/firmware.hex\" \
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-DUDS_HEX=\"$(P)/data/uds.hex\" \
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-DUDI_HEX=\"$(P)/data/udi.hex\" \
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--cc --exe --Mdir verilated --top-module application_fpga \
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$(filter %.v, $^) $(filter %.cc, $^)
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make -C verilated -f Vapplication_fpga.mk
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.PHONY: verilator
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#-------------------------------------------------------------------
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# Main FPGA build flow.
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# Synthesis. Place & Route. Bitstream generation.
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#-------------------------------------------------------------------
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synth.json: $(FPGA_SRC) $(VERILOG_SRCS) bram_fw.hex $(P)/data/uds.hex $(P)/data/udi.hex
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$(YOSYS_PATH)yosys -v3 -l synth.log -DBRAM_FW_SIZE=$(BRAM_FW_SIZE) \
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-DFIRMWARE_HEX=\"$(P)/bram_fw.hex\" \
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-DUDS_HEX=\"$(P)/data/uds.hex\" \
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-DUDI_HEX=\"$(P)/data/udi.hex\" \
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-p 'synth_ice40 -dsp -top application_fpga -json $@; write_verilog -attr2comment synth.v' \
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$(filter %.v, $^)
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application_fpga.asc: synth.json $(P)/data/$(PIN_FILE)
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$(NEXTPNR_PATH)nextpnr-ice40 --ignore-loops --up5k --package sg48 --json $< \
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--pcf $(P)/data/$(PIN_FILE) --asc $@
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application_fpga.bin: application_fpga.asc bram_fw.hex firmware.hex
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$(ICESTORM_PATH)icebram -v bram_fw.hex firmware.hex < $< > $<.tmp
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$(ICESTORM_PATH)icepack $<.tmp $@
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@-$(RM) $<.tmp
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application_fpga_testfw.bin: application_fpga.asc bram_fw.hex testfw.hex
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$(ICESTORM_PATH)icebram -v bram_fw.hex testfw.hex < $< > $<.tmp
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$(ICESTORM_PATH)icepack $<.tmp $@
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@-$(RM) $<.tmp
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#-------------------------------------------------------------------
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# post-synthesis functional simulation.
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#-------------------------------------------------------------------
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synth_tb.vvp: $(P)/tb/tb_application_fpga.v synth.json
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iverilog -o $@ -s tb_application_fpga synth.v $(P)/tb/tb_application_fpga.v \
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-DNO_ICE40_DEFAULT_ASSIGNMENTS $(ICE40_SIM_CELLS)
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chmod -x $@
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synth_sim: synth_tb.vvp
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vvp -N $<
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.PHONY: synth_sim
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synth_sim_vcd: synth_tb.vvp
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vvp -N $< +vcd
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.PHONY: synth_sim_vcd
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#-------------------------------------------------------------------
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# post-place and route functional simulation.
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#-------------------------------------------------------------------
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route.v: application_fpga.asc $(P)/data/$(PIN_FILE)
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icebox_vlog -L -n application_fpga -sp $(P)/data/$(PIN_FILE) $< > $@
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route_tb.vvp: route.v tb/tb_application_fpga.v
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iverilog -o $@ -s tb_application_fpga $^ $(ICE40_SIM_CELLS)
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chmod -x $@
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route_sim: route_tb.vvp
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vvp -N $<
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.PHONY: route_sim
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route_sim_vcd: route_tb.vvp
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vvp -N $< +vcd
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.PHONY: route_sim_vcd
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#-------------------------------------------------------------------
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# FPGA device programming.
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#-------------------------------------------------------------------
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prog_flash: application_fpga.bin
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sudo tillitis-iceprog $<
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.PHONY: prog_flash
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prog_flash_testfw: application_fpga_testfw.bin
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sudo tillitis-iceprog $<
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.PHONY: prog_flash_testfw
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#-------------------------------------------------------------------
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# Post build analysis.
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#-------------------------------------------------------------------
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timing: application_fpga.asc $(P)/data/$(PIN_FILE)
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$(ICESTORM_PATH)icetime -c 18 -tmd up5k -P sg48 -p $(P)/data/$(PIN_FILE) -t $<
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view: tb_application_fpga_vcd
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gtkwave $< application_fpga.gtkw
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#-------------------------------------------------------------------
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# Cleanup.
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#-------------------------------------------------------------------
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clean: clean_fw
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rm -f bram_fw.hex
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rm -f synth.{log,v,json} route.v application_fpga.{asc,bin,vcd} application_fpga_testfw.bin
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rm -f tb_application_fpga.vvp synth_tb.vvp route_tb.vvp
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rm -f *.vcd
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rm -f lint_issues.txt
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rm -rf verilated
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rm -f tools/tpt/*.hex
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rm -rf tools/tpt/__pycache__
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.PHONY: clean
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clean_fw:
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rm -f firmware.{elf,elf.map,bin,hex}
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rm -f $(FIRMWARE_OBJS)
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rm -f testfw.{elf,elf.map,bin,hex}
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rm -f $(TESTFW_OBJS)
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.PHONY: clean_fw
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#-------------------------------------------------------------------
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# Display info about targets.
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#-------------------------------------------------------------------
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help:
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@echo ""
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@echo "Build system for application_fpga FPGA design and firmware."
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@echo ""
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@echo "Supported targets:"
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@echo "------------------"
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@echo "all Build all targets."
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@echo "firmware.elf Build firmware ELF file."
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@echo "firmware.hex Build firmware converted to hex, to be included in bitstream."
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@echo "bram_fw.hex Build a fake BRAM file that will be filled in later after place-n-route."
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@echo "verilator Build Verilator simulation program"
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@echo "lint Run lint on Verilog source files."
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@echo "prog_flash Program device flash with FGPA bitstream including firmware (using the RPi Pico-based programmer)."
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@echo "prog_flash_testfw Program device flash as above, but with testfw."
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@echo "clean Delete all generated files."
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@echo "clean_fw Delete only generated files for firmware. Useful for fw devs."
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#=======================================================================
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# EOF Makefile
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#=======================================================================
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