mirror of
https://github.com/tillitis/tillitis-key1.git
synced 2024-09-30 05:15:40 +00:00
678 lines
20 KiB
Python
Executable File
678 lines
20 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# Copyright (C) 2021
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#
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# * Trammell Hudson <hudson@trmm.net>
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# * Matthew Mets https://github.com/cibomahto
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# * Peter Lawrence https://github.com/majbthrd
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#
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# Permission to use, copy, modify, and/or distribute this software for any
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# purpose with or without fee is hereby granted, provided that the above
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# copyright notice and this permission notice appear in all copies.
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#
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# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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#
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import usb_test
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import sys
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from time import sleep
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import os
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class Nvcm():
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# todo: add expected bitstream sizes
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id_table = {
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0x06: "ICE40LP8K / ICE40HX8K",
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0x07: "ICE40LP4K / ICE40HX4K",
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0x08: "ICE40LP1K / ICE40HX1K",
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0x09: "ICE40LP384",
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0x0E: "ICE40LP1K_SWG16",
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0x0F: "ICE40LP640_SWG16",
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0x10: "ICE5LP1K",
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0x11: "ICE5LP2K",
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0x12: "ICE5LP4K",
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0x14: "ICE40UL1K",
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0x15: "ICE40UL640",
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0x20: "ICE40UP5K",
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0x21: "ICE40UP3K",
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}
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def __init__(self, pins: dict, debug: bool = False) -> None:
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self.pins = pins
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self.debug = debug
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self.flasher = usb_test.ice40_flasher()
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self.flasher.gpio_put(self.pins['5v_en'], False)
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self.flasher.gpio_put(self.pins['crst'], False)
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# Configure pins for talking to ice40
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self.flasher.gpio_set_direction(pins['ss'], True)
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self.flasher.gpio_set_direction(pins['mosi'], True)
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self.flasher.gpio_set_direction(pins['sck'], True)
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self.flasher.gpio_set_direction(pins['miso'], False)
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self.flasher.gpio_set_direction(pins['5v_en'], True)
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self.flasher.gpio_set_direction(pins['crst'], True)
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self.flasher.gpio_set_direction(pins['cdne'], False)
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self.flasher.spi_pins_set(
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pins['sck'],
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pins['ss'],
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pins['mosi'],
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pins['miso']
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)
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def power_on(self) -> None:
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self.flasher.gpio_put(self.pins['5v_en'], True)
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def power_off(self) -> None:
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self.flasher.gpio_put(self.pins['5v_en'], False)
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def enable(self, cs: bool, reset: bool = True) -> None:
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# gpio.write(cs << cs_pin | reset << reset_pin)
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self.flasher.gpio_put(self.pins['ss'], cs)
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self.flasher.gpio_put(self.pins['crst'], reset)
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def sendhex(self, s: str) -> int:
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if self.debug and not s == "0500": # supress status check messages
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print("TX", s)
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x = bytes.fromhex(s)
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# b = dev.exchange(x, duplex=True, readlen=len(x))
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b = self.flasher.spi_bitbang(x, toggle_cs=False)
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if self.debug and not s == "0500":
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print("RX", b.hex())
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return int.from_bytes(b, byteorder='big')
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def sendhex_cs(self, s: str) -> bytes:
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if self.debug and not s == "0500":
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print("TX", s)
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x = bytes.fromhex(s)
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# b = dev.exchange(x, duplex=True, readlen=len(x))
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b = self.flasher.spi_bitbang(x)
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if self.debug and not s == "0500":
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print("RX", b.hex())
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return b
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def delay(self, count: int) -> None:
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# run the clock with no CS asserted
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# dev.exchange(b'\x00', duplex=True, readlen=count)
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self.sendhex('00' * count)
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def tck(self, count: int) -> None:
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self.delay(count >> 3)
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self.delay(count >> 3)
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self.delay(count >> 3)
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self.delay(count >> 3)
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self.delay(count >> 3)
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self.delay(count >> 3)
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def init(self) -> None:
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if self.debug:
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print("init")
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self.enable(True, True)
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self.enable(True, False) # reset high
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sleep(0.15)
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self.enable(False, False) # enable and reset high
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sleep(0.12)
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self.enable(False, True) # enable low, reset high
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sleep(0.12)
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self.enable(True, True) # enable and reset low
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sleep(0.12)
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def status_wait(self, count: int = 1000) -> None:
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for i in range(0, count):
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self.tck(5000)
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ret = self.sendhex_cs("0500")
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x = int.from_bytes(ret, byteorder='big')
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# print("x=%04x" %(x))
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if (x & 0x00c1) == 0:
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return
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raise Exception("status failed to clear")
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def command(self, cmd: str) -> None:
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self.sendhex_cs(cmd)
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self.status_wait()
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self.tck(8)
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def pgm_enable(self) -> None:
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self.command("06")
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def pgm_disable(self) -> None:
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self.command("04")
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def enable_access(self) -> None:
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# ! Shift in Access-NVCM instruction;
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# SMCInstruction[1] = 0x70807E99557E;
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self.command("7eaa997e010e")
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def read(self, address: int, length: int = 8, cmd: int = 0x03) -> int:
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"""Returns a big integer"""
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# enable(0)
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# sendhex("%02x%06x" % (cmd, address))
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# sendhex("00" * 9) # dummy bytes
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# x = 0
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# for i in range(0,length):
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# x = x << 8 | sendhex("00")
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# enable(1)
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msg = ''
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msg += ("%02x%06x" % (cmd, address))
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msg += ("00" * 9) # dummy bytes
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msg += ("00" * length) # read
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ret = self.sendhex_cs(msg)
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x = 0
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for i in range(0, length):
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x = x << 8 | ret[i + 4 + 9]
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return x
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def read_bytes(self, address: int, length: int = 8) -> bytes:
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"""Returns a byte array of the contents"""
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return self.read(address, length).to_bytes(length, byteorder="big")
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def write(self, address: int, data: str, cmd: int = 0x02) -> None:
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self.sendhex_cs("%02x%06x" % (cmd, address) + data)
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try:
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self.status_wait()
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except Exception as e:
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raise Exception("WRITE FAILED: cmd=%02x address=%06x data=%s" %
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(cmd, address, data))
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self.tck(8)
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def bank_select(self, bank: int) -> None:
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self.write(cmd=0x83, address=0x000025, data="%02x" % (bank))
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def select_nvcm(self) -> None:
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# ! Shift in Restore Access-NVCM instruction;
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# SDR 40 TDI(0x00A40000C1);
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self.bank_select(0x00)
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def select_trim(self) -> None:
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# ! Shift in Trim setup-NVCM instruction;
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# SDR 40 TDI(0x08A40000C1);
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self.bank_select(0x10)
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def select_sig(self) -> None:
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# ! Shift in Access Silicon Signature instruction;
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# IDInstruction[1] = 0x04A40000C1;
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# SDR 40 TDI(IDInstruction[1]);
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self.bank_select(0x20)
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def read_trim(self) -> int:
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# ! Shift in Access-NVCM instruction;
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# SMCInstruction[1] = 0x70807E99557E;
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self.enable_access()
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# ! Shift in READ_RF(0x84) instruction;
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# SDR 104 TDI(0x00000000000000000004000021);
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x = self.read(cmd=0x84, address=0x000020, length=8)
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self.tck(8)
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# print("FSM Trim Register %x" % (x))
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self.select_nvcm()
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return x
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def write_trim(self, data: str) -> None:
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# ! Setup Programming Parameter in Trim Registers;
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# ! Shift in Trim setup-NVCM instruction;
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# TRIMInstruction[1] = 0x000000430F4FA80004000041;
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self.write(cmd=0x82, address=0x000020, data=data)
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def nvcm_enable(self) -> None:
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if self.debug:
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print("enable")
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# ! Shift in Access-NVCM instruction;
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# SMCInstruction[1] = 0x70807E99557E;
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self.enable_access()
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# ! Setup Reading Parameter in Trim Registers;
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# ! Shift in Trim setup-NVCM instruction;
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# TRIMInstruction[1] = 0x000000230000000004000041;
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if self.debug:
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print("setup_nvcm")
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self.write_trim("00000000c4000000")
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def enable_trim(self) -> None:
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# ! Setup Programming Parameter in Trim Registers;
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# ! Shift in Trim setup-NVCM instruction;
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# TRIMInstruction[1] = 0x000000430F4FA80004000041;
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self.write_trim("0015f2f0c2000000")
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def trim_blank_check(self) -> bool:
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print("NVCM Trim_Parameter_OTP blank check")
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self.select_trim()
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x = self.read(0x000020, 1)
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self.select_nvcm()
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if x != 0:
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print("NVCM Trim_Parameter_OTP Block is not blank. (%02x)" % x)
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return False
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return True
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def blank_check(self, total_fuse: int) -> bool:
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self.select_nvcm()
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status = True
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print("NVCM main memory blank check")
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contents = self.read_bytes(0x000000, total_fuse)
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for i in range(0, total_fuse):
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x = contents[i]
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if self.debug:
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print("%08x: %02x" % (i, x))
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if x != 0:
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print(
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"%08x: NVCM Main Memory Block is not blank." %
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(i), file=sys.stderr)
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status = False
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self.select_nvcm()
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return status
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def program(self, rows: list[str]) -> None:
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print("NVCM Program main memory")
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self.select_nvcm()
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self.enable_trim()
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self.pgm_enable()
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status = True
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i = 0
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for row in rows:
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if i % 1024 == 0:
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print("%6d / %6d bytes" % (i, len(rows) * 8))
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i += 8
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try:
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self.command(row)
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except Exception as e:
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raise Exception("programming failed, row:", row)
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self.pgm_disable()
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def write_trim_pages(self, lock_bits: str) -> None:
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self.select_nvcm()
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self.enable_trim()
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self.select_trim()
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self.pgm_enable()
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# ! Program Security Bit row 1;
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# ! Shift in PAGEPGM instruction;
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# SDR 96 TDI(0x000000008000000C04000040);
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# ! Program Security Bit row 2;
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# SDR 96 TDI(0x000000008000000C06000040);
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# ! Program Security Bit row 3;
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# SDR 96 TDI(0x000000008000000C05000040);
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# ! Program Security Bit row 4;
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# SDR 96 TDI(0x00000000800000C07000040);
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self.write(0x000020, lock_bits)
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self.write(0x000060, lock_bits)
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self.write(0x0000a0, lock_bits)
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self.write(0x0000e0, lock_bits)
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self.pgm_disable()
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# verify a read back
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x = self.read(0x000020, 8)
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self.select_nvcm()
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lock_bits_int = int(lock_bits, 16)
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if x & lock_bits_int != lock_bits_int:
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raise Exception(
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"Failed to write trim lock bits: %016x != expected %016x" %
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(x, lock_bits_int))
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print("New state %016x" % (x))
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def trim_secure(self) -> None:
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print("NVCM Secure")
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trim = self.read_trim()
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if (trim >> 60) & 0x3 != 0:
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print("NVCM already secure? trim=%016x" % (trim), file=sys.stderr)
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self.write_trim_pages("3000000100000000")
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def trim_program(self) -> None:
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print("NVCM Program Trim_Parameter_OTP")
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self.write_trim_pages("0015f2f1c4000000")
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def info(self) -> None:
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self.select_sig()
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sig1 = self.read(0x000000, 8)
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self.select_sig()
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sig2 = self.read(0x000008, 8)
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# have to switch back to nvcm bank before switching to trim?
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self.select_nvcm()
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trim = self.read_trim()
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self.select_nvcm()
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self.select_trim()
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trim0 = self.read(0x000020, 8)
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self.select_trim()
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trim1 = self.read(0x000060, 8)
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self.select_trim()
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trim2 = self.read(0x0000a0, 8)
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self.select_trim()
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trim3 = self.read(0x0000e0, 8)
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self.select_nvcm()
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secured = ((trim >> 60) & 0x3)
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device_id = (sig1 >> 56) & 0xFF
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print("Device: %s (%02x) secure=%d" % (
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self.id_table.get(device_id, "Unknown"),
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device_id,
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secured
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))
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print("Sig 0: %016x" % (sig1))
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print("Sig 1: %016x" % (sig2))
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print("TrimRF: %016x" % (trim))
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print("Trim 0: %016x" % (trim0))
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print("Trim 1: %016x" % (trim1))
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print("Trim 2: %016x" % (trim2))
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print("Trim 3: %016x" % (trim3))
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def read_file(self, filename: str) -> None:
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self.select_nvcm()
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total_fuse = 104090
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contents = b''
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for offset in range(0, total_fuse, 8):
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if offset % 1024 == 0:
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print("%6d / %6d bytes" % (offset, total_fuse))
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contents += self.read_bytes(offset, 8)
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if filename == '-':
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with os.fdopen(sys.stdout.fileno(), "wb", closefd=False) as f:
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f.write(contents)
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f.flush()
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else:
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with open(filename, "wb") as f:
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f.write(contents)
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f.flush()
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#
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# bistream to NVCM command conversion is based on majbthrd's work in
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# https://github.com/YosysHQ/icestorm/pull/272
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#
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def bitstream2nvcm(bitstream: bytes) -> list[str]:
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# ensure that the file starts with the correct bistream preamble
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for origin in range(0, len(bitstream)):
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if bitstream[origin:origin + 4] == bytes.fromhex('7EAA997E'):
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break
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if origin == len(bitstream):
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raise Exception("Preamble not found")
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print("Found preamable at %08x" % (origin), file=sys.stderr)
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# there might be stuff in the header with vendor tools,
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# but not usually in icepack produced output, so ignore it for now
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# todo: what is the correct size?
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rows = []
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for pos in range(origin, len(bitstream), 8):
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row = bitstream[pos:pos + 8]
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# pad out to 8-bytes
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row += b'\0' * (8 - len(row))
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if row == bytes(8):
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# skip any all-zero entries in the bistream
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continue
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# NVCM addressing is very weird
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addr = pos - origin
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nvcm_addr = int(addr / 328) * 4096 + (addr % 328)
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rows += ["02 %06x %s" % (nvcm_addr, row.hex())]
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return rows
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def sleep_flash(pins: dict) -> None:
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""" Put the SPI bootloader flash in deep sleep mode"""
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flasher = usb_test.ice40_flasher()
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# Disable board power
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flasher.gpio_put(pins['5v_en'], False)
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flasher.gpio_set_direction(pins['5v_en'], True)
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# Pull CRST low to prevent FPGA from starting
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flasher.gpio_set_direction(pins['crst'], True)
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flasher.gpio_put(pins['crst'], False)
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# Enable board power
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flasher.gpio_put(pins['5v_en'], True)
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# Configure pins for talking to flash
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flasher.gpio_set_direction(pins['ss'], True)
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flasher.gpio_set_direction(pins['mosi'], False)
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flasher.gpio_set_direction(pins['sck'], True)
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flasher.gpio_set_direction(pins['miso'], True)
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flasher.spi_pins_set(
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pins['sck'],
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pins['ss'],
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pins['miso'],
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pins['mosi']
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)
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flasher.spi_bitbang(bytes([0xAB]))
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# Confirm we can talk to flash
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data = flasher.spi_bitbang(bytes([0x9f, 0, 0]))
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print('flash ID while awake:', ' '.join(
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['{:02x}'.format(b) for b in data]))
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assert (data == bytes([0xff, 0xef, 0x40]))
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# Test that the flash will ignore a sleep command that doesn't start on
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# the first byte
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flasher.spi_bitbang(bytes([0, 0xb9]))
|
|
|
|
# Confirm we can talk to flash
|
|
data = flasher.spi_bitbang(bytes([0x9f, 0, 0]))
|
|
|
|
print('flash ID while awake:', ' '.join(
|
|
['{:02x}'.format(b) for b in data]))
|
|
assert (data == bytes([0xff, 0xef, 0x40]))
|
|
|
|
# put the flash to sleep
|
|
flasher.spi_bitbang(bytes([0xb9]))
|
|
|
|
# Confirm flash is asleep
|
|
data = flasher.spi_bitbang(bytes([0x9f, 0, 0]))
|
|
|
|
print('flash ID while asleep:', ' '.join(
|
|
['{:02x}'.format(b) for b in data]))
|
|
assert (data == bytes([0xff, 0xff, 0xff]))
|
|
|
|
|
|
if __name__ == "__main__":
|
|
|
|
import argparse
|
|
|
|
parser = argparse.ArgumentParser()
|
|
|
|
parser.add_argument('--port',
|
|
type=str,
|
|
default='ftdi://::/1',
|
|
help='FTDI port of the form ftdi://::/1')
|
|
|
|
parser.add_argument('-v', '--verbose',
|
|
dest='verbose',
|
|
action='store_true',
|
|
help='Show debug information and serial read/writes')
|
|
|
|
parser.add_argument(
|
|
'-f',
|
|
'--sleep_flash',
|
|
dest='sleep_flash',
|
|
action='store_true',
|
|
help='Put an attached SPI flash chip in deep sleep before programming FPGA')
|
|
|
|
parser.add_argument(
|
|
'-b',
|
|
'--boot',
|
|
dest='do_boot',
|
|
action='store_true',
|
|
help='Deassert the reset line to allow the FPGA to boot')
|
|
|
|
parser.add_argument('-i', '--info',
|
|
dest='read_info',
|
|
action='store_true',
|
|
help='Read chip ID, trim and other info')
|
|
|
|
parser.add_argument('--read',
|
|
dest='read_file',
|
|
type=str,
|
|
default=None,
|
|
help='Read contents of NVCM')
|
|
|
|
parser.add_argument(
|
|
'--write',
|
|
dest='write_file',
|
|
type=str,
|
|
default=None,
|
|
help='bitstream file to write to NVCM (warning: not reversable!)')
|
|
|
|
parser.add_argument('--ignore-blank',
|
|
dest='ignore_blank',
|
|
action='store_true',
|
|
help='Proceed even if the chip is not blank')
|
|
|
|
parser.add_argument(
|
|
'--secure',
|
|
dest='set_secure',
|
|
action='store_true',
|
|
help='Set security bits to prevent modification (warning: not reversable!')
|
|
|
|
parser.add_argument(
|
|
'--my-design-is-good-enough',
|
|
dest='good_enough',
|
|
action='store_true',
|
|
help='Enable the dangerous commands --write and --secure')
|
|
|
|
args = parser.parse_args()
|
|
|
|
if not args.good_enough \
|
|
and (args.write_file or args.set_secure):
|
|
print("Are you sure your design is good enough?", file=sys.stderr)
|
|
exit(1)
|
|
|
|
# Instantiate a SPI controller, with separately managed CS line
|
|
# spi = SpiController()
|
|
|
|
# Configure the first interface (IF/1) of the FTDI device as a SPI controller
|
|
# spi.configure(args.port)
|
|
|
|
# Get a port to a SPI device w/ /CS on A*BUS3 and SPI mode 0 @ 12MHz
|
|
# the CS line is not used in this case
|
|
# dev = spi.get_port(cs=0, freq=12E6, mode=0)
|
|
|
|
# reset_pin = 7
|
|
# cs_pin = 4
|
|
|
|
# Get GPIO port to manage the CS and RESET pins
|
|
# gpio = spi.get_gpio()
|
|
# gpio.set_direction(1 << reset_pin | 1 << cs_pin, 1 << reset_pin | 1 << cs_pin)
|
|
|
|
# Enable power to the FPGA, then set both reset and CS pins high
|
|
|
|
# # Reset pin values
|
|
# for pin in tp1_pins:
|
|
# flasher.gpio_set_direction(tp1_pins[pin], False)
|
|
|
|
tp1_pins = {
|
|
'5v_en': 7,
|
|
'sck': 10,
|
|
'mosi': 11,
|
|
'ss': 12,
|
|
'miso': 13,
|
|
'crst': 14,
|
|
'cdne': 15
|
|
}
|
|
|
|
if args.sleep_flash:
|
|
sleep_flash(tp1_pins)
|
|
|
|
nvcm = Nvcm(tp1_pins, debug=args.verbose)
|
|
nvcm.power_on()
|
|
|
|
# # Turn on ICE40 in CRAM boot mode
|
|
nvcm.init()
|
|
nvcm.nvcm_enable()
|
|
|
|
if args.read_info:
|
|
nvcm.info()
|
|
|
|
if args.write_file:
|
|
with open(args.write_file, "rb") as f:
|
|
bitstream = f.read()
|
|
print("read %d bytes" % (len(bitstream)))
|
|
cmds = bitstream2nvcm(bitstream)
|
|
if not cmds:
|
|
exit(1)
|
|
|
|
if not args.ignore_blank:
|
|
nvcm.trim_blank_check() or exit(1)
|
|
# how much should we check?
|
|
nvcm.blank_check(0x100) or exit(1)
|
|
|
|
# this is it!
|
|
nvcm.program(cmds)
|
|
|
|
# update the trim to boot from nvcm
|
|
nvcm.trim_program()
|
|
|
|
if args.read_file:
|
|
# read back after writing to the NVCM
|
|
nvcm.read_file(args.read_file)
|
|
|
|
if args.set_secure:
|
|
nvcm.trim_secure()
|
|
|
|
if args.do_boot:
|
|
# hold reset low for half a second
|
|
nvcm.enable(True, False)
|
|
sleep(0.5)
|
|
nvcm.enable(True, True)
|