93 lines
2.6 KiB
Verilog
93 lines
2.6 KiB
Verilog
//======================================================================
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//
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// spram.v
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// -------
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// Module that encapsulates two of the SPRAM blocks in the Lattice
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// iCE40UP 5K device. This creates a single 32-bit wide,
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// 64 kByte large memory.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2022 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module spram(
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input wire clk,
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input wire rst_n,
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input wire cs,
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input wire [03 : 0] wen,
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input wire [13 : 0] addr,
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input wire [31 : 0] wdata,
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output wire ready,
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output wire [31 : 0] rdata
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);
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//----------------------------------------------------------------
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// Registers and wires.
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//----------------------------------------------------------------
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reg ready_reg;
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reg ready_new;
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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assign ready = ready_reg;
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//----------------------------------------------------------------
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// SPRAM instances.
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//----------------------------------------------------------------
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SB_SPRAM256KA spram0(
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.ADDRESS(addr[13:0]),
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.DATAIN(wdata[15:0]),
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.MASKWREN({wen[1], wen[1], wen[0], wen[0]}),
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.WREN(wen[1]|wen[0]),
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.CHIPSELECT(cs),
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.CLOCK(clk),
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.STANDBY(1'b0),
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.SLEEP(1'b0),
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.POWEROFF(1'b1),
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.DATAOUT(rdata[15:0])
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);
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SB_SPRAM256KA spram1(
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.ADDRESS(addr[13:0]),
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.DATAIN(wdata[31:16]),
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.MASKWREN({wen[3], wen[3], wen[2], wen[2]}),
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.WREN(wen[3]|wen[2]),
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.CHIPSELECT(cs),
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.CLOCK(clk),
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.STANDBY(1'b0),
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.SLEEP(1'b0),
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.POWEROFF(1'b1),
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.DATAOUT(rdata[31:16])
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);
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//----------------------------------------------------------------
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// reg_update.
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//
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// Posedge triggered with synchronous, active low reset.
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// This simply creates a one cycle access delay to allow the
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// memory access to complete.
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//----------------------------------------------------------------
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always @(posedge clk)
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begin : reg_update
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if (!rst_n) begin
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ready_reg <= 1'h0;
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end
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else begin
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ready_reg <= cs;
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end
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end
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endmodule // spram
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//======================================================================
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// EOF spram.v
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//======================================================================
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