68 lines
2.0 KiB
Verilog
68 lines
2.0 KiB
Verilog
//======================================================================
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//
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// rom..v
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// ------
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// Firmware ROM module. Implemented using Embedded Block RAM
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// in the FPGA.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2022 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module rom(
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input wire clk,
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input wire reset_n,
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input wire cs,
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input wire [11 : 0] address,
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output wire [31 : 0] read_data,
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output wire ready
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);
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//----------------------------------------------------------------
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// Registers, memories with associated wires.
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//----------------------------------------------------------------
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// Size of the sysMem Embedded Block RAM (EBR) memory primarily
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// used for code storage (ROM). The size is number of
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// 32-bit words. Each EBR is 4kbit in size, and (at most)
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// 16-bit wide. Thus means that we use pairs of EBRs, and
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// each pair store 256 32bit words.
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// The size of the EBR allocated to memory must match the
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// size of the firmware file generated by the Makefile.
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localparam EBR_MEM_SIZE = `BRAM_FW_SIZE;
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reg [31 : 0] memory [0 : (EBR_MEM_SIZE - 1)];
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initial $readmemh(`FIRMWARE_HEX, memory);
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reg [31 : 0] rom_rdata;
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reg rom_ready;
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//----------------------------------------------------------------
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// Concurrent assignments of ports.
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//----------------------------------------------------------------
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assign read_data = rom_rdata;
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assign ready = rom_ready;
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//----------------------------------------------------------------
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// rom_logic
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//----------------------------------------------------------------
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always @*
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begin : rom_logic
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rom_rdata = memory[address];
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rom_ready = cs;
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end
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endmodule // rom
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//======================================================================
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// EOF rom..v
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//======================================================================
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