73 lines
1.9 KiB
Verilog
73 lines
1.9 KiB
Verilog
//======================================================================
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//
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// reset_gen.v
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// -----------
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// Reset generator for iCE40 based systems.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2022 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module reset_gen #(parameter RESET_CYCLES = 200)
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(
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input wire clk,
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output wire rst_n
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);
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//----------------------------------------------------------------
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// Registers with associated wires.
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//----------------------------------------------------------------
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reg [7 : 0] rst_ctr_reg = 8'h0;
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reg [7 : 0] rst_ctr_new;
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reg rst_ctr_we;
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reg rst_n_reg = 1'h0;
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reg rst_n_new;
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//----------------------------------------------------------------
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// Concurrent assignment.
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//----------------------------------------------------------------
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assign rst_n = rst_n_reg;
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//----------------------------------------------------------------
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// reg_update.
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//----------------------------------------------------------------
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always @(posedge clk)
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begin : reg_update
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rst_n_reg <= rst_n_new;
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if (rst_ctr_we)
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rst_ctr_reg <= rst_ctr_new;
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end
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//----------------------------------------------------------------
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// rst_logic.
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//----------------------------------------------------------------
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always @*
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begin : rst_logic
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rst_n_new = 1'h1;
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rst_ctr_new = 8'h0;
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rst_ctr_we = 1'h0;
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if (rst_ctr_reg < RESET_CYCLES) begin
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rst_n_new = 1'h0;
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rst_ctr_new = rst_ctr_reg + 1'h1;
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rst_ctr_we = 1'h1;
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end
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end
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endmodule // reset_gen
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//======================================================================
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// EOF reset_gen.v
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//======================================================================
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