76 lines
2.7 KiB
Verilog
76 lines
2.7 KiB
Verilog
//======================================================================
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//
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// firo.v
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// ------
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// Fibonacci Ring Oscillator with state sampling.
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// The Fibonacci depth is 10 bits, and the bits are always sampled.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2022 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module firo(
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input wire clk,
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output wire entropy
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);
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parameter POLY = 10'b1111111111;
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//----------------------------------------------------------------
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// Registers and wires.
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//----------------------------------------------------------------
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reg entropy_reg;
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wire [10 : 0] f;
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//---------------------------------------------------------------
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// Combinational loop inverters.
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//---------------------------------------------------------------
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(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv1 (.I0(f[0]), .O(f[1]));
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(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv2 (.I0(f[1]), .O(f[2]));
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(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv3 (.I0(f[2]), .O(f[3]));
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(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv4 (.I0(f[3]), .O(f[4]));
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(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv5 (.I0(f[4]), .O(f[5]));
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(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv6 (.I0(f[5]), .O(f[6]));
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(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv7 (.I0(f[6]), .O(f[7]));
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(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv8 (.I0(f[7]), .O(f[8]));
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(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv9 (.I0(f[8]), .O(f[9]));
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(* keep *) SB_LUT4 #(.LUT_INIT(1'b1)) osc_inv10 (.I0(f[9]), .O(f[10]));
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//---------------------------------------------------------------
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// parameterized feedback logic.
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//---------------------------------------------------------------
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assign f[0] = (POLY[0] & f[1]) ^ (POLY[1] & f[2]) ^
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(POLY[2] & f[3]) ^ (POLY[3] & f[4]) ^
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(POLY[4] & f[5]) ^ (POLY[5] & f[6]) ^
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(POLY[6] & f[7]) ^ (POLY[7] & f[8]) ^
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(POLY[8] & f[9]) ^ (POLY[9] & f[10]);
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//----------------------------------------------------------------
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// Concurrent connectivity for ports etc.
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//----------------------------------------------------------------
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assign entropy = entropy_reg;
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//---------------------------------------------------------------
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// reg_update
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//---------------------------------------------------------------
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always @(posedge clk)
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begin : reg_update
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entropy_reg <= ^f;
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end
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endmodule // firo
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//======================================================================
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// EOF firo.v
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//======================================================================
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