294 lines
7.6 KiB
Verilog
294 lines
7.6 KiB
Verilog
//======================================================================
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//
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// tb_timer.v
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// -----------
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// Testbench for the timer top level wrapper.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2022 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module tb_timer();
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//----------------------------------------------------------------
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// Internal constant and parameter definitions.
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//----------------------------------------------------------------
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parameter DEBUG = 0;
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parameter DUMP_WAIT = 0;
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parameter CLK_HALF_PERIOD = 1;
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parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
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localparam ADDR_NAME0 = 8'h00;
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localparam ADDR_NAME1 = 8'h01;
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localparam ADDR_VERSION = 8'h02;
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localparam ADDR_CTRL = 8'h08;
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localparam CTRL_NEXT_BIT = 0;
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localparam ADDR_STATUS = 8'h09;
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localparam STATUS_READY_BIT = 0;
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localparam ADDR_CONFIG = 8'h0a;
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localparam CONFIG_ENCDEC_BIT = 0;
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localparam ADDR_KEY0 = 8'h10;
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localparam ADDR_KEY1 = 8'h11;
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localparam ADDR_KEY2 = 8'h12;
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localparam ADDR_KEY3 = 8'h13;
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localparam ADDR_BLOCK0 = 8'h20;
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localparam ADDR_BLOCK1 = 8'h21;
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localparam ADDR_RESULT0 = 8'h30;
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localparam ADDR_RESULT1 = 8'h31;
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//----------------------------------------------------------------
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// Register and Wire declarations.
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//----------------------------------------------------------------
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reg [31 : 0] cycle_ctr;
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reg [31 : 0] error_ctr;
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reg [31 : 0] tc_ctr;
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reg tb_monitor;
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reg tb_clk;
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reg tb_reset_n;
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reg tb_cs;
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reg tb_we;
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reg [7 : 0] tb_address;
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reg [31 : 0] tb_write_data;
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wire [31 : 0] tb_read_data;
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reg [31 : 0] read_data;
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//----------------------------------------------------------------
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// Device Under Test.
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//----------------------------------------------------------------
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timer dut(
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.clk(tb_clk),
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.reset_n(tb_reset_n),
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.cs(tb_cs),
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.we(tb_we),
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.address(tb_address),
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.write_data(tb_write_data),
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.read_data(tb_read_data)
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);
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//----------------------------------------------------------------
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// clk_gen
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//
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// Always running clock generator process.
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//----------------------------------------------------------------
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always
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begin : clk_gen
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#CLK_HALF_PERIOD;
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tb_clk = !tb_clk;
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end // clk_gen
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//----------------------------------------------------------------
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// sys_monitor()
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//
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// An always running process that creates a cycle counter and
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// conditionally displays information about the DUT.
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//----------------------------------------------------------------
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always
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begin : sys_monitor
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cycle_ctr = cycle_ctr + 1;
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#(CLK_PERIOD);
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if (tb_monitor)
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begin
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dump_dut_state();
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end
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end
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//----------------------------------------------------------------
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// dump_dut_state()
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//
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// Dump the state of the dump when needed.
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//----------------------------------------------------------------
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task dump_dut_state;
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begin
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$display("State of DUT");
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$display("------------");
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$display("Cycle: %08d", cycle_ctr);
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$display("");
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end
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endtask // dump_dut_state
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//----------------------------------------------------------------
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// reset_dut()
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//
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// Toggle reset to put the DUT into a well known state.
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//----------------------------------------------------------------
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task reset_dut;
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begin
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$display("--- Toggle reset.");
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tb_reset_n = 0;
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#(2 * CLK_PERIOD);
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tb_reset_n = 1;
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end
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endtask // reset_dut
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//----------------------------------------------------------------
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// display_test_result()
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//
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// Display the accumulated test results.
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//----------------------------------------------------------------
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task display_test_result;
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begin
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if (error_ctr == 0)
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begin
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$display("--- All %02d test cases completed successfully", tc_ctr);
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end
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else
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begin
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$display("--- %02d tests completed - %02d test cases did not complete successfully.",
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tc_ctr, error_ctr);
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end
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end
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endtask // display_test_result
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//----------------------------------------------------------------
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// init_sim()
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//
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// Initialize all counters and testbed functionality as well
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// as setting the DUT inputs to defined values.
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//----------------------------------------------------------------
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task init_sim;
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begin
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cycle_ctr = 0;
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error_ctr = 0;
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tc_ctr = 0;
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tb_monitor = 0;
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tb_clk = 1'h0;
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tb_reset_n = 1'h1;
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tb_cs = 1'h0;
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tb_we = 1'h0;
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tb_address = 8'h0;
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tb_write_data = 32'h0;
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end
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endtask // init_sim
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//----------------------------------------------------------------
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// write_word()
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//
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// Write the given word to the DUT using the DUT interface.
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//----------------------------------------------------------------
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task write_word(input [11 : 0] address,
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input [31 : 0] word);
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begin
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if (DEBUG)
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begin
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$display("--- Writing 0x%08x to 0x%02x.", word, address);
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$display("");
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end
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tb_address = address;
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tb_write_data = word;
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tb_cs = 1;
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tb_we = 1;
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#(2 * CLK_PERIOD);
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tb_cs = 0;
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tb_we = 0;
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end
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endtask // write_word
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//----------------------------------------------------------------
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// read_word()
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//
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// Read a data word from the given address in the DUT.
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// the word read will be available in the global variable
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// read_data.
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//----------------------------------------------------------------
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task read_word(input [11 : 0] address);
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begin
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tb_address = address;
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tb_cs = 1;
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tb_we = 0;
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#(CLK_PERIOD);
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read_data = tb_read_data;
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tb_cs = 0;
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if (DEBUG)
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begin
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$display("--- Reading 0x%08x from 0x%02x.", read_data, address);
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$display("");
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end
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end
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endtask // read_word
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//----------------------------------------------------------------
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// wait_ready()
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//
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// Wait for the ready flag to be set in dut.
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//----------------------------------------------------------------
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task wait_ready;
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begin : wready
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read_word(ADDR_STATUS);
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while (read_data == 0)
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read_word(ADDR_STATUS);
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end
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endtask // wait_ready
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//----------------------------------------------------------------
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// test1()
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//----------------------------------------------------------------
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task test1;
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begin
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tc_ctr = tc_ctr + 1;
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$display("");
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$display("--- test1: started.");
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$display("--- test1: completed.");
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$display("");
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end
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endtask // tes1
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//----------------------------------------------------------------
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// timer_test
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//----------------------------------------------------------------
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initial
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begin : timer_test
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$display("");
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$display(" -= Testbench for timer started =-");
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$display(" =============================");
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$display("");
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init_sim();
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reset_dut();
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test1();
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display_test_result();
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$display("");
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$display(" -= Testbench for timer started =-");
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$display(" =============================");
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$display("");
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$finish;
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end // timer_test
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endmodule // tb_timer
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//======================================================================
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// EOF tb_timer.v
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//======================================================================
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