327 lines
8.2 KiB
Verilog
327 lines
8.2 KiB
Verilog
//======================================================================
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//
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// mta1.v
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// ------
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// Top level information, debug and control core for the mta1 design.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2022 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module mta1(
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input wire clk,
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input wire reset_n,
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output wire fw_app_mode,
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output wire led_r,
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output wire led_g,
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output wire led_b,
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input wire gpio1,
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input wire gpio2,
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output wire gpio3,
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output wire gpio4,
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input wire cs,
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input wire we,
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input wire [7 : 0] address,
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input wire [31 : 0] write_data,
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output wire [31 : 0] read_data,
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output wire ready
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);
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//----------------------------------------------------------------
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// Internal constant and parameter definitions.
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//----------------------------------------------------------------
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localparam ADDR_NAME0 = 8'h00;
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localparam ADDR_NAME1 = 8'h01;
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localparam ADDR_VERSION = 8'h02;
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localparam ADDR_SWITCH_APP = 8'h08;
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localparam ADDR_LED = 8'h09;
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localparam LED_R_BIT = 2;
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localparam LED_G_BIT = 1;
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localparam LED_B_BIT = 0;
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localparam ADDR_GPIO = 8'h0a;
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localparam GPIO1_BIT = 0;
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localparam GPIO2_BIT = 1;
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localparam GPIO3_BIT = 2;
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localparam GPIO4_BIT = 3;
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localparam ADDR_APP_START = 8'h0c;
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localparam ADDR_APP_SIZE = 8'h0d;
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localparam ADDR_DEBUG = 8'h10;
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localparam ADDR_CDI_FIRST = 8'h20;
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localparam ADDR_CDI_LAST = 8'h27;
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localparam ADDR_UDI_FIRST = 8'h30;
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localparam ADDR_UDI_LAST = 8'h31;
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localparam MTA1_NAME0 = 32'h6d746131; // "mta1"
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localparam MTA1_NAME1 = 32'h6d6b6466; // "mkdf"
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localparam MTA1_VERSION = 32'h00000004;
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//----------------------------------------------------------------
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// Registers including update variables and write enable.
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//----------------------------------------------------------------
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reg [31 : 0] cdi_mem [0 : 7];
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reg [31 : 0] cdi_mem_we;
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reg [31 : 0] udi_mem [0 : 1];
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initial $readmemh(`UDI_HEX, udi_mem);
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reg switch_app_reg;
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reg switch_app_we;
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reg [2 : 0] led_reg;
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reg led_we;
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reg [1 : 0] gpio1_reg;
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reg [1 : 0] gpio2_reg;
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reg gpio3_reg;
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reg gpio3_we;
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reg gpio4_reg;
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reg gpio4_we;
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reg [31 : 0] app_start_reg;
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reg app_start_we;
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reg [31 : 0] app_size_reg;
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reg app_size_we;
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reg [31 : 0] debug_reg;
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reg debug_we;
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//----------------------------------------------------------------
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// Wires.
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//----------------------------------------------------------------
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/* verilator lint_off UNOPTFLAT */
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reg [31 : 0] tmp_read_data;
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reg tmp_ready;
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/* verilator lint_on UNOPTFLAT */
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//----------------------------------------------------------------
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// Concurrent connectivity for ports etc.
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//----------------------------------------------------------------
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assign read_data = tmp_read_data;
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assign ready = tmp_ready;
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assign fw_app_mode = switch_app_reg;
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assign gpio3 = gpio3_reg;
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assign gpio4 = gpio4_reg;
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//----------------------------------------------------------------
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// Module instance.
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//----------------------------------------------------------------
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SB_RGBA_DRV #(
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.CURRENT_MODE("0b1"), // half-current mode
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.RGB0_CURRENT("0b000001"), // 2 mA
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.RGB1_CURRENT("0b000001"), // 2 mA
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.RGB2_CURRENT("0b000001") // 2 mA
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) RGBA_DRV (
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.RGB0(led_r),
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.RGB1(led_g),
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.RGB2(led_b),
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.RGBLEDEN(1'h1),
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.RGB0PWM(led_reg[LED_R_BIT]),
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.RGB1PWM(led_reg[LED_G_BIT]),
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.RGB2PWM(led_reg[LED_B_BIT]),
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.CURREN(1'b1)
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);
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//----------------------------------------------------------------
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// reg_update
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//----------------------------------------------------------------
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always @ (posedge clk)
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begin : reg_update
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if (!reset_n) begin
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switch_app_reg <= 1'h0;
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led_reg <= 3'h6;
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gpio1_reg <= 2'h0;
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gpio2_reg <= 2'h0;
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gpio3_reg <= 1'h0;
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gpio4_reg <= 1'h0;
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app_start_reg <= 32'h0;
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app_size_reg <= 32'h0;
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debug_reg <= 32'h0;
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cdi_mem[0] <= 32'h0;
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cdi_mem[1] <= 32'h0;
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cdi_mem[2] <= 32'h0;
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cdi_mem[3] <= 32'h0;
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cdi_mem[4] <= 32'h0;
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cdi_mem[5] <= 32'h0;
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cdi_mem[6] <= 32'h0;
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cdi_mem[7] <= 32'h0;
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end
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else begin
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gpio1_reg[0] <= gpio1;
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gpio1_reg[1] <= gpio1_reg[0];
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gpio2_reg[0] <= gpio2;
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gpio2_reg[1] <= gpio2_reg[0];
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if (switch_app_we) begin
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switch_app_reg <= 1'h1;
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end
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if (led_we) begin
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led_reg <= write_data[2 : 0];
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end
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if (gpio3_we) begin
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gpio3_reg <= write_data[GPIO3_BIT];
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end
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if (gpio4_we) begin
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gpio4_reg <= write_data[GPIO4_BIT];
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end
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if (app_start_we) begin
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app_start_reg <= write_data;
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end
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if (app_size_we) begin
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app_size_reg <= write_data;
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end
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if (debug_we) begin
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debug_reg <= write_data;
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end
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if (cdi_mem_we) begin
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cdi_mem[address[2 : 0]] <= write_data;
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end
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end
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end // reg_update
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//----------------------------------------------------------------
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// api
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//----------------------------------------------------------------
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always @*
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begin : api
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switch_app_we = 1'h0;
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led_we = 1'h0;
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gpio3_we = 1'h0;
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gpio4_we = 1'h0;
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app_start_we = 1'h0;
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app_size_we = 1'h0;
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debug_we = 1'h0;
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cdi_mem_we = 1'h0;
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cdi_mem_we = 1'h0;
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tmp_read_data = 32'h00000000;
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tmp_ready = 1'h0;
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if (cs) begin
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tmp_ready = 1'h1;
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if (we) begin
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if (address == ADDR_SWITCH_APP) begin
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switch_app_we = 1'h1;
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end
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if (address == ADDR_LED) begin
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led_we = 1'h1;
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end
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if (address == ADDR_GPIO) begin
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gpio3_we = 1'h1;
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gpio4_we = 1'h1;
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end
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if (address == ADDR_APP_START) begin
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if (!switch_app_reg) begin
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app_start_we = 1'h1;
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end
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end
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if (address == ADDR_APP_SIZE) begin
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if (!switch_app_reg) begin
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app_size_we = 1'h1;
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end
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end
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if (address == ADDR_DEBUG) begin
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debug_we = 1'h1;
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end
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if ((address >= ADDR_CDI_FIRST) && (address <= ADDR_CDI_LAST)) begin
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if (!switch_app_reg) begin
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cdi_mem_we = 1'h1;
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end
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end
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end
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else begin
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if (address == ADDR_NAME0) begin
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tmp_read_data = MTA1_NAME0;
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end
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if (address == ADDR_NAME1) begin
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tmp_read_data = MTA1_NAME1;
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end
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if (address == ADDR_VERSION) begin
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tmp_read_data = MTA1_VERSION;
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end
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if (address == ADDR_SWITCH_APP) begin
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tmp_read_data = {32{switch_app_reg}};
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end
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if (address == ADDR_LED) begin
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tmp_read_data = {29'h0, led_reg};
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end
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if (address == ADDR_GPIO) begin
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tmp_read_data = {28'h0, gpio4_reg, gpio3_reg,
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gpio2_reg[1], gpio1_reg[1]};
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end
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if (address == ADDR_APP_START) begin
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tmp_read_data = app_start_reg;
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end
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if (address == ADDR_APP_SIZE) begin
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tmp_read_data = app_size_reg;
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end
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if (address == ADDR_DEBUG) begin
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tmp_read_data = debug_reg;
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end
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if ((address >= ADDR_CDI_FIRST) && (address <= ADDR_CDI_LAST)) begin
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tmp_read_data = cdi_mem[address[2 : 0]];
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end
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if ((address >= ADDR_UDI_FIRST) && (address <= ADDR_UDI_LAST)) begin
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tmp_read_data = udi_mem[address[0]];
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end
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end
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end
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end // api
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endmodule // mta1
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//======================================================================
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// EOF mta1.v
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//======================================================================
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