mirror of
https://github.com/tillitis/tillitis-key1.git
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c35e7680ea
Silence lint on intentional combinatinal loops Use better instance names, and a single lint pragma for all macros Remove unused pointer update signals Silence lint on wires where not all bits are used Change fw_app_mode to be an input port to allow access control Remove redundant, unused wire mem_busy Add lint pragma to ignore debug register only enabled by a define Remove clk and reset_n ports from the ROM Adding note and lint pragma for rom address width Fix incorrect register widths in uart_core Assign all 16 bits in LUT config Silence lint warnings on macro instances Correct bit extraction for core addresses to be eight bits wide Correct the bit width of cdi_mem_we wire Add specific output file for logging lint issues Correct bit width of tmp_ready to match one bit ready port
178 lines
5.0 KiB
Verilog
178 lines
5.0 KiB
Verilog
//======================================================================
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//
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// uart_fifo.v
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// -----------
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// FIFO for rx and tx data buffering in the UART.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (c) 2022, Tillitis AB
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//
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// Redistribution and use in source and binary forms, with or
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// without modification, are permitted provided that the following
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// conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//======================================================================
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module uart_fifo(
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input wire clk,
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input wire reset_n,
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input wire in_syn,
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input wire [7 : 0] in_data,
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output wire in_ack,
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output wire out_syn,
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output wire [7 : 0] out_data,
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input wire out_ack
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);
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//----------------------------------------------------------------
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// Registers including update variables and write enable.
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//----------------------------------------------------------------
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reg [7 : 0] fifo_mem [0 : 255];
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reg fifo_mem_we;
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reg [7: 0] in_ptr_reg;
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reg [7: 0] in_ptr_new;
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reg in_ptr_we;
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reg [7: 0] out_ptr_reg;
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reg [7: 0] out_ptr_new;
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reg out_ptr_we;
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reg [7: 0] byte_ctr_reg;
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reg [7: 0] byte_ctr_new;
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reg byte_ctr_inc;
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reg byte_ctr_dec;
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reg byte_ctr_we;
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reg in_ack_reg;
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reg in_ack_new;
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//----------------------------------------------------------------
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// Concurrent connectivity for ports etc.
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//----------------------------------------------------------------
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assign in_ack = in_ack_reg;
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assign out_syn = |byte_ctr_reg;
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assign out_data = fifo_mem[out_ptr_reg];
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//----------------------------------------------------------------
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// reg_update
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//----------------------------------------------------------------
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always @ (posedge clk)
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begin: reg_update
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if (!reset_n) begin
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in_ptr_reg <= 8'h0;
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out_ptr_reg <= 8'h0;
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byte_ctr_reg <= 8'h0;
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in_ack_reg <= 1'h0;
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end
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else begin
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in_ack_reg <= in_ack_new;
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if (fifo_mem_we) begin
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fifo_mem[in_ptr_reg] <= in_data;
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end
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if (in_ptr_we) begin
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in_ptr_reg <= in_ptr_new;
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end
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if (out_ptr_we) begin
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out_ptr_reg <= out_ptr_new;
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end
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if (byte_ctr_we) begin
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byte_ctr_reg <= byte_ctr_new;
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end
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end
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end // reg_update
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//----------------------------------------------------------------
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// byte_ctr
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//----------------------------------------------------------------
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always @*
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begin : byte_ctr
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byte_ctr_new = 8'h0;
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byte_ctr_we = 1'h0;
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if ((byte_ctr_inc) && (!byte_ctr_dec)) begin
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byte_ctr_new = byte_ctr_reg + 1'h1;
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byte_ctr_we = 1'h1;
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end
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else if ((!byte_ctr_inc) && (byte_ctr_dec)) begin
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byte_ctr_new = byte_ctr_reg - 1'h1;
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byte_ctr_we = 1'h1;
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end
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end
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//----------------------------------------------------------------
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// in_logic
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//----------------------------------------------------------------
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always @*
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begin : in_logic
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fifo_mem_we = 1'h0;
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in_ack_new = 1'h0;
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byte_ctr_inc = 1'h0;
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in_ptr_new = in_ptr_reg + 1'h1;
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in_ptr_we = 1'h0;
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if ((in_syn) && (!in_ack) && (byte_ctr_reg < 8'hff)) begin
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fifo_mem_we = 1'h1;
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in_ack_new = 1'h1;
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byte_ctr_inc = 1'h1;
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in_ptr_we = 1'h1;
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end
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end
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//----------------------------------------------------------------
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// out_logic
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//----------------------------------------------------------------
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always @*
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begin : out_logic
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byte_ctr_dec = 1'h0;
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out_ptr_new = out_ptr_reg + 1'h1;
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out_ptr_we = 1'h0;
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if ((out_ack) && (byte_ctr_reg > 8'h0)) begin
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byte_ctr_dec = 1'h1;
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out_ptr_we = 1'h1;
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end
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end
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endmodule // uart_fifo
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//======================================================================
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// EOF uart_fifo.v
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//======================================================================
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