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https://github.com/tillitis/tillitis-key1.git
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112 lines
3.0 KiB
Verilog
112 lines
3.0 KiB
Verilog
//======================================================================
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//
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// fw_ram.v
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// --------
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// A 256 x 32 RAM (1024 bytes) for use by the FW. The memory has
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// support for mode based access control.
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2022 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module fw_ram(
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input wire clk,
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input wire reset_n,
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input wire fw_app_mode,
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input wire cs,
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input wire [3 : 0] we,
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input wire [7 : 0] address,
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input wire [31 : 0] write_data,
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output wire [31 : 0] read_data,
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output wire ready
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);
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//----------------------------------------------------------------
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// Registers and wires.
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//----------------------------------------------------------------
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reg [31 : 0] tmp_read_data;
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reg [31 : 0] mem_read_data;
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reg ready_reg;
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reg fw_app_cs;
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//----------------------------------------------------------------
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// Concurrent assignment of ports.
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//----------------------------------------------------------------
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assign read_data = tmp_read_data;
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assign ready = ready_reg;
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assign fw_app_cs = cs && ~fw_app_mode;
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//----------------------------------------------------------------
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// Block RAM instances.
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//----------------------------------------------------------------
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SB_RAM40_4K fw_ram0(
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.RDATA(mem_read_data[15 : 0]),
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.RADDR({3'h0, address}),
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.RCLK(clk),
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.RCLKE(1'h1),
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.RE(fw_app_cs),
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.WADDR({3'h0, address}),
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.WCLK(clk),
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.WCLKE(1'h1),
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.WDATA(write_data[15 : 0]),
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.WE((|we && fw_app_cs)),
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.MASK({{8{~we[1]}}, {8{~we[0]}}})
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);
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SB_RAM40_4K fw_ram1(
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.RDATA(mem_read_data[31 : 16]),
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.RADDR({3'h0, address}),
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.RCLK(clk),
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.RCLKE(1'h1),
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.RE(fw_app_cs),
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.WADDR({3'h0, address}),
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.WCLK(clk),
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.WCLKE(1'h1),
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.WDATA(write_data[31 : 16]),
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.WE((|we && fw_app_cs)),
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.MASK({{8{~we[3]}}, {8{~we[2]}}})
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);
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//----------------------------------------------------------------
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// reg_update
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//----------------------------------------------------------------
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always @(posedge clk)
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begin : reg_update
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if (!reset_n) begin
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ready_reg <= 1'h0;
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end
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else begin
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ready_reg <= cs;
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end
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end
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//----------------------------------------------------------------
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// read_mux
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//----------------------------------------------------------------
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always @*
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begin : read_mux;
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if (fw_app_cs) begin
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tmp_read_data = mem_read_data;
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end else begin
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tmp_read_data = 32'h0;
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end
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end
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endmodule // fw_ram
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//======================================================================
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// EOF fw_ram.v
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//======================================================================
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