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Joachim Strömbergson 610522201b
Remove AXI and WB interface modules
2022-09-27 09:48:54 +02:00
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rtl Remove AXI and WB interface modules 2022-09-27 09:48:54 +02:00
LICENSE Make initial public release 2022-09-19 08:51:11 +02:00
README.md Make initial public release 2022-09-19 08:51:11 +02:00

README.md

PicoRV32 - A Size-Optimized RISC-V CPU

This is a local copy of the PicoRV32 RISC-V CPU core.