mirror of https://github.com/tillitis/tillitis-key1.git synced 2024-12-20 21:34:28 -05:00

History

Joachim Strömbergson c35e7680ea Squashed commit of the following: Silence lint on intentional combinatinal loops Use better instance names, and a single lint pragma for all macros Remove unused pointer update signals Silence lint on wires where not all bits are used Change fw_app_mode to be an input port to allow access control Remove redundant, unused wire mem_busy Add lint pragma to ignore debug register only enabled by a define Remove clk and reset_n ports from the ROM Adding note and lint pragma for rom address width Fix incorrect register widths in uart_core Assign all 16 bits in LUT config Silence lint warnings on macro instances Correct bit extraction for core addresses to be eight bits wide Correct the bit width of cdi_mem_we wire Add specific output file for logging lint issues Correct bit width of tmp_ready to match one bit ready port	2022-10-06 13:23:30 +02:00
..
rtl	Squashed commit of the following:	2022-10-06 13:23:30 +02:00
README.md	Make initial public release	2022-09-19 08:51:11 +02:00

Joachim Strömbergson c35e7680ea

Silence lint on intentional combinatinal loops
    Use better instance names, and a single lint pragma for all macros
    Remove unused pointer update signals
    Silence lint on wires where not all bits are used
    Change fw_app_mode to be an input port to allow access control
    Remove redundant, unused wire mem_busy
    Add lint pragma to ignore debug register only enabled by a define
    Remove clk and reset_n ports from the ROM
    Adding note and lint pragma for rom address width
    Fix incorrect register widths in uart_core
    Assign all 16 bits in LUT config
    Silence lint warnings on macro instances
    Correct bit extraction for core addresses to be eight bits wide
    Correct the bit width of cdi_mem_we wire
    Add specific output file for logging lint issues
    Correct bit width of tmp_ready to match one bit ready port

2022-10-06 13:23:30 +02:00

rtl

Squashed commit of the following:

2022-10-06 13:23:30 +02:00

README.md

Make initial public release

2022-09-19 08:51:11 +02:00

README.md

mta1

Introduction

Top level core that provides chip info, debug support and chip level control.