mirror of
https://github.com/tillitis/tillitis-key1.git
synced 2024-10-01 01:45:38 -04:00
c35e7680ea
Silence lint on intentional combinatinal loops Use better instance names, and a single lint pragma for all macros Remove unused pointer update signals Silence lint on wires where not all bits are used Change fw_app_mode to be an input port to allow access control Remove redundant, unused wire mem_busy Add lint pragma to ignore debug register only enabled by a define Remove clk and reset_n ports from the ROM Adding note and lint pragma for rom address width Fix incorrect register widths in uart_core Assign all 16 bits in LUT config Silence lint warnings on macro instances Correct bit extraction for core addresses to be eight bits wide Correct the bit width of cdi_mem_we wire Add specific output file for logging lint issues Correct bit width of tmp_ready to match one bit ready port
91 lines
3.3 KiB
Verilog
91 lines
3.3 KiB
Verilog
//======================================================================
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//
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// garo.v
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// ------
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// GaloisRing Oscillator with state sampling.
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// The Galois depth is 11 bits, and the bits are always sampled.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2022 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module garo(
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input wire clk,
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output wire entropy
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);
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parameter POLY = 11'b11111111111;
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//----------------------------------------------------------------
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// Registers and wires.
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//----------------------------------------------------------------
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reg entropy_reg;
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/* verilator lint_off UNOPTFLAT */
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wire [11 : 0] g;
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wire [11 : 0] gp;
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/* verilator lint_on UNOPTFLAT */
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//---------------------------------------------------------------
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// Combinational loop inverters.
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//---------------------------------------------------------------
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/* verilator lint_off PINMISSING */
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(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv1 (.I0(g[0]), .O(gp[0]));
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(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv2 (.I0(g[1]), .O(gp[1]));
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(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv3 (.I0(g[2]), .O(gp[2]));
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(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv4 (.I0(g[3]), .O(gp[3]));
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(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv5 (.I0(g[4]), .O(gp[4]));
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(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv6 (.I0(g[5]), .O(gp[5]));
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(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv7 (.I0(g[6]), .O(gp[6]));
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(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv8 (.I0(g[7]), .O(gp[7]));
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(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv9 (.I0(g[8]), .O(gp[8]));
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(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv10 (.I0(g[9]), .O(gp[9]));
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(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv11 (.I0(g[10]), .O(gp[10]));
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(* keep *) SB_LUT4 #(.LUT_INIT(16'h1)) osc_inv12 (.I0(g[11]), .O(gp[11]));
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/* verilator lint_on PINMISSING */
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//---------------------------------------------------------------
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// parameterized feedback logic.
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//---------------------------------------------------------------
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assign g[11] = gp[0];
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assign g[10] = gp[11] ^ (POLY[10] & gp[0]);
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assign g[9] = gp[10] ^ (POLY[9] & gp[0]);
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assign g[8] = gp[9] ^ (POLY[8] & gp[0]);
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assign g[7] = gp[8] ^ (POLY[7] & gp[0]);
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assign g[6] = gp[7] ^ (POLY[6] & gp[0]);
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assign g[5] = gp[6] ^ (POLY[5] & gp[0]);
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assign g[4] = gp[5] ^ (POLY[4] & gp[0]);
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assign g[3] = gp[4] ^ (POLY[3] & gp[0]);
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assign g[2] = gp[3] ^ (POLY[2] & gp[0]);
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assign g[1] = gp[2] ^ (POLY[1] & gp[0]);
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assign g[0] = gp[1] ^ (POLY[0] & gp[0]);
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//----------------------------------------------------------------
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// Concurrent connectivity for ports etc.
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//----------------------------------------------------------------
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assign entropy = entropy_reg;
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//---------------------------------------------------------------
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// reg_update
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//---------------------------------------------------------------
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always @(posedge clk)
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begin : reg_update
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entropy_reg <= ^g;
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end
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endmodule // garo
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//======================================================================
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// EOF garo.v
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//======================================================================
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