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https://github.com/tillitis/tillitis-key1.git
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60 lines
1.4 KiB
Makefile
60 lines
1.4 KiB
Makefile
TARGET = top
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VERILOG_FILES = \
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top.v
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PIN_CONFIG_FILE = app.pcf
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default: $(TARGET).bin
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$(TARGET).json: $(VERILOG_FILES)
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yosys \
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-q \
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-p "synth_ice40 -abc2 -relut -top ${TARGET} -json $(TARGET).json" \
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-l $(TARGET)-yosys.log \
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$(VERILOG_FILES)
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TARGET_MODULE = top
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view-ideal:
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yosys -p 'read_verilog ${VERILOG_FILES}; proc; opt; select ${TARGET_MODULE}; show -format dot -viewer xdot -pause' &
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view-real:
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yosys -p 'read_verilog ${VERILOG_FILES}; proc; opt; synth_ice40; show -format dot -viewer xdot -pause' &
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$(TARGET).asc: $(TARGET).json $(PIN_CONFIG_FILE)
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nextpnr-ice40 \
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--up5k \
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--package sg48 \
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--json $(TARGET).json \
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--pcf $(PIN_CONFIG_FILE) \
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--asc $(TARGET).asc \
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-l $(TARGET)-nextpnr.log
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$(TARGET).bin: $(TARGET).asc
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icepack $(TARGET).asc $(TARGET).bin
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stats: $(TARGET).json $(TARGET).asc
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sed -n '/=== top ===/,/6\.28/p' $(TARGET)-yosys.log
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sed -n '/Info: Device utilisation/,/Info: Placed/p' $(TARGET)-nextpnr.log
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fgrep 'Info: Max frequency for clock' $(TARGET)-nextpnr.log
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lint: $(VERILOG_FILES)
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verilator --lint-only -Wall -Wno-DECLFILENAME -Ihw_blocks $(VERILOG_FILES)
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.PHONY: flash
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flash: ${TARGET}.bin
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iceprog -I A ${TARGET}.bin
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.PHONY: load
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load: ${TARGET}.bin
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iceprog -S -I A ${TARGET}.bin
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.PHONY: clean
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clean:
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$(RM) -f \
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$(TARGET).json \
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$(TARGET).asc \
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$(TARGET)-yosys.log \
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$(TARGET)-nextpnr.log \
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$(TARGET).bin
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