mirror of
https://github.com/tillitis/tillitis-key1.git
synced 2025-02-06 18:15:31 -05:00
3ccdf8fc0f
- Add CTS signals let the FPGA and CH552 signal each other that
it is OK send UART data.
- Update the CH552 rx and frame handling logic.
- Fix minor spelling errors and indentation
268 lines
6.7 KiB
C
268 lines
6.7 KiB
C
/********************************** (C) COPYRIGHT *******************************
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* File Name : Debug.C
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* Author : WCH
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* Version : V1.0
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* Date : 2017/01/20
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* Description : CH554 DEBUG Interface
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CH554 main frequency modification, delay function definition
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Serial port 0 and serial port 1 initialization
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Serial port 0 and serial port 1 transceiver subfunctions
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Watchdog initialization
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*******************************************************************************/
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#include <stdint.h>
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#include "ch554.h"
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#include "debug.h"
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/*******************************************************************************
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* Function Name : CfgFsys( )
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* Description : CH554 clock selection and configuration function, Fsys 6MHz is used by default, FREQ_SYS can be passed
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CLOCK_CFG configuration, the formula is as follows:
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Fsys = (Fosc * 4 / (CLOCK_CFG & MASK_SYS_CK_SEL); the specific clock needs to be configured by yourself
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*******************************************************************************/
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void CfgFsys()
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{
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SAFE_MOD = 0x55;
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SAFE_MOD = 0xAA;
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// CLOCK_CFG |= bOSC_EN_XT; // Enable external crystal
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// CLOCK_CFG & = ~ bOSC_EN_INT; // Turn off the internal crystal
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#if FREQ_SYS == 32000000
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CLOCK_CFG = CLOCK_CFG & ~ MASK_SYS_CK_SEL | 0x07; // 32MHz
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#elif FREQ_SYS == 24000000
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CLOCK_CFG = CLOCK_CFG & ~ MASK_SYS_CK_SEL | 0x06; // 24MHz
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#elif FREQ_SYS == 16000000
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CLOCK_CFG = CLOCK_CFG & ~ MASK_SYS_CK_SEL | 0x05; // 16MHz
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#elif FREQ_SYS == 12000000
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CLOCK_CFG = CLOCK_CFG & ~ MASK_SYS_CK_SEL | 0x04; // 12MHz
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#elif FREQ_SYS == 6000000
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CLOCK_CFG = CLOCK_CFG & ~ MASK_SYS_CK_SEL | 0x03; // 6MHz
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#elif FREQ_SYS == 3000000
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CLOCK_CFG = CLOCK_CFG & ~ MASK_SYS_CK_SEL | 0x02; // 3MHz
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#elif FREQ_SYS == 750000
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CLOCK_CFG = CLOCK_CFG & ~ MASK_SYS_CK_SEL | 0x01; // 750KHz
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#elif FREQ_SYS == 187500
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CLOCK_CFG = CLOCK_CFG & ~ MASK_SYS_CK_SEL | 0x00; // 187.5MHz
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#else
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#warning FREQ_SYS invalid or not set
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#endif
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SAFE_MOD = 0x00;
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}
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/*******************************************************************************
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* Function Name : mDelayus(UNIT16 n)
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* Description : us delay function
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* Input : UNIT16 n
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* Output : None
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* Return : None
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*******************************************************************************/
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void mDelayuS(uint16_t n) // Delay in uS
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{
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#ifdef FREQ_SYS
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#if FREQ_SYS <= 6000000
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n >>= 2;
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#endif
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#if FREQ_SYS <= 3000000
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n >>= 2;
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#endif
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#if FREQ_SYS <= 750000
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n >>= 4;
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#endif
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#endif
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while (n) { // Total = 12~13 Fsys cycles, 1uS @Fsys=12MHz
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++SAFE_MOD; // 2 Fsys cycles, for higher Fsys, add operation here
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#ifdef FREQ_SYS
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#if FREQ_SYS >= 14000000
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++SAFE_MOD;
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#endif
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#if FREQ_SYS >= 16000000
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++SAFE_MOD;
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#endif
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#if FREQ_SYS >= 18000000
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++SAFE_MOD;
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#endif
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#if FREQ_SYS >= 20000000
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++SAFE_MOD;
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#endif
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#if FREQ_SYS >= 22000000
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++SAFE_MOD;
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#endif
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#if FREQ_SYS >= 24000000
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++SAFE_MOD;
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#endif
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#if FREQ_SYS >= 26000000
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++SAFE_MOD;
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#endif
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#if FREQ_SYS >= 28000000
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++SAFE_MOD;
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#endif
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#if FREQ_SYS >= 30000000
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++SAFE_MOD;
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#endif
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#if FREQ_SYS >= 32000000
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++SAFE_MOD;
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#endif
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#endif
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--n;
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}
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}
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/*******************************************************************************
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* Function Name : mDelayms(UNIT16 n)
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* Description : ms delay function
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* Input : UNIT16 n
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* Output : None
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* Return : None
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*******************************************************************************/
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void mDelaymS(uint16_t n) // Delay in mS
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{
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while (n) {
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#ifdef DELAY_MS_HW
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while ( ( TKEY_CTRL & bTKC_IF ) == 0 );
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while ( TKEY_CTRL & bTKC_IF );
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#else
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mDelayuS(1000);
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#endif
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--n;
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}
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}
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#if SDCC < 370
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void putchar(char c)
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{
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while (!TI); /* assumes UART is initialized */
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TI = 0;
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SBUF = c;
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}
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char getchar(void)
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{
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while(!RI); /* assumes UART is initialized */
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RI = 0;
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return SBUF;
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}
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#else
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int putchar(int c)
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{
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while (!TI); /* assumes UART is initialized */
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TI = 0;
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SBUF = c & 0xFF;
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return c;
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}
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int getchar(void)
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{
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while(!RI); /* assumes UART is initialized */
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RI = 0;
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return SBUF;
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}
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#endif
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// Set pin p1.4 and p1.5 to GPIO output mode.
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void gpio_init()
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{
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// p1.4
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P1_MOD_OC &= ~0x10;
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P1_DIR_PU |= 0x10;
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// p1.5
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P1_MOD_OC &= ~0x20;
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P1_DIR_PU |= 0x20;
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}
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void gpio_set(uint8_t pin)
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{
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switch (pin) {
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case 0x10: // p1.4
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P1 |= 0x10;
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break;
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case 0x20: // p1.5
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P1 |= 0x20;
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break;
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default: // do nothing, unsupported pin.
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break;
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}
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}
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void gpio_unset(uint8_t pin)
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{
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switch (pin) {
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case 0x10:
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P1 &= ~0x10;
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break;
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case 0x20:
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P1 &= ~0x20;
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break;
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default: // do nothing, unsupported pin.
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break;
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}
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}
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uint8_t gpio_get(uint8_t pin)
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{
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uint8_t ret = 0;
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switch (pin) {
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case 0x10: // p1.4
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ret = P1 & 0x10;
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break;
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case 0x20: // p1.5
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ret = P1 & 0x20;
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break;
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default: // do nothing, unsupported pin.
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ret = 0xff;
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break;
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}
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return ret;
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}
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// Set pin p1.4 to GPIO input mode. (FPGA_CTS)
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void gpio_init_p1_4_in()
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{
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// p1.4
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P1_MOD_OC &= ~0x10; // Output Mode: 0 = Push-pull output, 1 = Open-drain output
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P1_DIR_PU &= ~0x10; // Port Direction Control and Pull-up Enable Register:
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// Push-pull output mode:
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// 0 = Input.
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// 1 = Output
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// Open-drain output mode:
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// 0 = Pull-up resistor disabled
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// 1 = Pull-up resistor enabled
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}
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// Read status of pin 1.4
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uint8_t gpio_p1_4_get(void)
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{
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return (P1 & 0x10); // p1.4
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}
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// Set pin p1.5 to GPIO output mode. (CH552_CTS)
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void gpio_init_p1_5_out()
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{
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// p1.5
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P1_MOD_OC &= ~0x20; // Output Mode: 0 = Push-pull output, 1 = Open-drain output
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P1_DIR_PU |= 0x20; // Port Direction Control and Pull-up Enable Register:
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// Push-pull output mode:
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// 0 = Input.
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// 1 = Output
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// Open-drain output mode:
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// 0 = Pull-up resistor disabled
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// 1 = Pull-up resistor enabled
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}
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// Set p1.5 high
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void gpio_p1_5_set(void)
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{
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P1 |= 0x20; // p1.4
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}
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// Set p1.5 low
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void gpio_p1_5_unset(void)
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{
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P1 &= ~0x20;
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}
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