Daniel Jobson 3d7a97ecbc fpga: remove the API for configuring the UART core ... This removes the possibility to configure the bit rate, data bits and stop bits at runtime from the API. This reduces the usage of LCs with ~4%. It is still possible to configure the core before building. Update digest of application_fpga.bin.sha256		2024-11-26 15:24:12 +01:00
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clk_reset_gen	FPGA: Format verilog code	2024-10-22 12:04:19 +02:00
fw_ram	Doc: fix typo of system mode in readme	2024-11-13 14:13:02 +01:00
picorv32	FPGA: Ignore warnings about blocking assignment in clocked processes	2024-06-17 15:37:13 +02:00
ram	Doc: move implementation details of RAM scrambling to RAM core	2024-11-20 15:48:49 +01:00
rom	Fix typo	2024-11-14 16:35:50 +01:00
timer	FPGA: Format verilog code	2024-10-22 12:04:19 +02:00
tk1	doc: Harmonize preformatted in tk1 core	2024-11-15 15:01:31 +01:00
touch_sense	FPGA: Format verilog code	2024-10-22 12:04:19 +02:00
trng	Change "rosc" references to "trng"	2024-11-14 16:35:51 +01:00
uart	fpga: remove the API for configuring the UART core	2024-11-26 15:24:12 +01:00
uds	Harmonize the naming of firmware and app mode.	2024-11-12 15:13:59 +01:00