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tillitis-key/hw/application_fpga/data
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Mikael Ågren 1e20dba10a
fpga/ch552: Swap fpga_cts and ch552_cts pins 
The FPGA uwg30 package cannot use B3 as an input when an instance of
SB_PLL40_CORE is placed. We swap fpga_cts and ch552_cts to make B3 (from
here on fpga_cts) an output.

For more info check out:
FPGA-TN-02052-1-4-iCE40-sysCLOCK-PLL-Design-User-Guide.pdf chapter "5.1
PLL Placement Rules"
2025-05-19 08:55:26 +02:00
..
application_fpga_mta1_usb_dev.pcf Rename to TK1 2022-10-26 09:20:02 +02:00
application_fpga_tk1.pcf fpga/ch552: Swap fpga_cts and ch552_cts pins 2025-05-19 08:55:26 +02:00
application_fpga_tk1_uwg30.pcf fpga/ch552: Swap fpga_cts and ch552_cts pins 2025-05-19 08:55:26 +02:00
udi.hex Make initial public release 2022-09-19 08:51:11 +02:00
uds.hex Use different byte values in test UDS words 2023-03-28 09:26:23 +02:00