clk_reset_gen
|
FPGA: Format verilog code
|
2024-10-22 12:04:19 +02:00 |
fw_ram
|
FPGA: Format verilog code
|
2024-10-22 12:04:19 +02:00 |
ram
|
FPGA: Format verilog code
|
2024-10-22 12:04:19 +02:00 |
rom
|
FPGA: Format verilog code
|
2024-10-22 12:04:19 +02:00 |
timer
|
FPGA: Format verilog code
|
2024-10-22 12:04:19 +02:00 |
tk1
|
FPGA: Format verilog code
|
2024-10-22 12:04:19 +02:00 |
touch_sense
|
FPGA: Format verilog code
|
2024-10-22 12:04:19 +02:00 |
trng
|
FPGA: Format verilog code
|
2024-10-22 12:04:19 +02:00 |
uart
|
FPGA: Format verilog code
|
2024-10-22 12:04:19 +02:00 |
uds
|
FPGA: Format verilog code
|
2024-10-22 12:04:19 +02:00 |