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5535323b06
A proof-of-concept of enabling PicoRV32 interrupts. Two interrupt
sources, which can be triggered by writes to memory addresses, are
added. The design has only been simulated, not run on hardware.
Synthesis:
Ice40 LC utilization is 93% (4934/5280) when built using tkey-builder:4
Simulation:
A `tb_application_fpga_irqpoc` target is added. Running `make
tb_application_fpga_irqpoc` creates `tb_application_fpga_sim.fst` which
can be inspected in GTKWave or Surfer.
Firmware:
A simple firmware is added in `fw/irqpoc`. It enables both interrupts
and triggers each interrupt once.
Custom PicoRV32 instructions are located in `custom_ops.S`. It is
imported from upstream PicoRV32 commit:
70f3c33ac8
43 lines
1.2 KiB
ArmAsm
43 lines
1.2 KiB
ArmAsm
/*
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* Copyright (C) 2022, 2023 - Tillitis AB
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* SPDX-License-Identifier: GPL-2.0-only
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*/
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#include "custom_ops.S" // PicoRV32 custom instructions
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.section ".text.init"
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.globl _start
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_start:
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j init
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.=0x10 // IRQ handler at fixed address 0x10
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irq_handler:
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// PicoRV32 stores the IRQ bitmask in x4.
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// If bit 31 is 1: IRQ31 was triggered.
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// If bit 30 is 1: IRQ30 was triggered.
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nop // NOPs are not necessary. Only added to make it easier to find
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nop // when simulating.
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nop
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picorv32_retirq_insn() // Return from interrupt
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.=0x20 // Setting location of init to 0x20. Makes it easier to find when
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// simulating.
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init:
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li t0, 0x3fffffff // IRQ31 & IRQ30 mask
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picorv32_maskirq_insn(zero, t0) // Enable IRQs
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li t0, 0xe1000000 // IRQ31 trigger address
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sw zero, 0(t0) // Raise IRQ by writing to interrupt trigger address.
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// Writing any data triggers an interrupt.
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li t0, 0xe0000000 // IRQ30 trigger address
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sw zero, 0(t0) // Raise IRQ by writing to interrupt trigger address.
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// Writing any data triggers an interrupt.
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loop:
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j loop
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.align 4 // Padding to please makehex.py which requires even 4-byte file
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// sizes.
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