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tillitis-key/hw/application_fpga/core/uart
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Joachim Strömbergson 9ce2b8a84a
Only accept tx data when the core is ready 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2023-01-02 13:10:40 +01:00
..
rtl Only accept tx data when the core is ready 2023-01-02 13:10:40 +01:00
tb Make initial public release 2022-09-19 08:51:11 +02:00
LICENSE Make initial public release 2022-09-19 08:51:11 +02:00
README.md Make initial public release 2022-09-19 08:51:11 +02:00

README.md

uart

A simple universal asynchronous receiver/transmitter (UART) core implemented in Verilog.

Status

The core is completed and has been used in several FPGA designs.