mirror of
https://github.com/tillitis/tillitis-key1.git
synced 2024-08-01 16:12:47 +00:00
103 lines
2.2 KiB
Verilog
103 lines
2.2 KiB
Verilog
module top (
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input INT_CLOCK,
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output reg HOST_SS,
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input HOST_SCK,
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output reg HOST_MOSI,
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input HOST_MISO,
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output reg HOST_EXTRA1,
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input HOST_EXTRA2,
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output reg HOST_EXTRA3,
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input HOST_EXTRA4,
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output reg HOST_EXTRA5,
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input HOST_EXTRA6,
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output reg HOST_EXTRA7,
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input HOST_EXTRA8,
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output reg HOST_EXTRA9,
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input HOST_EXTRA10,
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output INT_GPIO1,
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output INT_GPIO2,
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output INT_GPIO3,
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output INT_GPIO4,
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output RGB0,
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output RGB1,
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output RGB2
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);
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//############ Feedback test ############################################
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always @(posedge INT_CLOCK) begin
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HOST_SS <= ~HOST_SS;
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end
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always @(posedge HOST_SCK) begin
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HOST_MOSI <= ~HOST_MOSI;
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end
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always @(posedge HOST_MISO) begin
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HOST_EXTRA1 <= ~HOST_EXTRA1;
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end
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always @(posedge HOST_EXTRA2) begin
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HOST_EXTRA3 <= ~HOST_EXTRA3;
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end
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always @(posedge HOST_EXTRA4) begin
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HOST_EXTRA5 <= ~HOST_EXTRA5;
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end
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always @(posedge HOST_EXTRA6) begin
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HOST_EXTRA7 <= ~HOST_EXTRA7;
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end
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always @(posedge HOST_EXTRA8) begin
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HOST_EXTRA9 <= ~HOST_EXTRA9;
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end
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reg [10:0] slow_led;
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always @(posedge HOST_EXTRA10) begin
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slow_led <= slow_led + 1;
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end
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SB_RGBA_DRV #(
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.CURRENT_MODE("0b1"), // half-current mode
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.RGB0_CURRENT("0b000001"), // 2 mA
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.RGB1_CURRENT("0b000001"), // 2 mA
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.RGB2_CURRENT("0b000001") // 2 mA
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) RGBA_DRV (
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.RGB0(RGB0),
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.RGB1(RGB1),
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.RGB2(RGB2),
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.RGBLEDEN(1'b1),
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.RGB0PWM(slow_led[10]),
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.RGB1PWM(slow_led[9]),
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.RGB2PWM(slow_led[8]),
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.CURREN(1'b1)
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);
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//############ Clock / Reset ############################################
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wire clk;
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// Configure the HFOSC
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SB_HFOSC #(
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.CLKHF_DIV("0b01") // 00: 48MHz, 01: 24MHz, 10: 12MHz, 11: 6MHz
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) u_hfosc (
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.CLKHFPU(1'b1),
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.CLKHFEN(1'b1),
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.CLKHF(clk)
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);
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//############ GPIO tests ###############################################
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assign INT_GPIO1 = clk;
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assign INT_GPIO2 = INT_CLOCK;
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assign INT_GPIO3 = HOST_EXTRA8;
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assign INT_GPIO4 = HOST_EXTRA10;
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endmodule
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