Joachim Strömbergson 8c476e19c3 FPGA: Add new SPI access control logis ... New logic looks at instruction execution from a defined trampoline address to enable stateful SPI access. The access is disabled as soon as an instruction is executed from any address in RAM. Signed-off-by: Joachim Strömbergson <joachim@assured.se>		2024-08-22 11:43:39 +02:00
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application_fpga.v	FPGA: Add new SPI access control logis	2024-08-22 11:43:39 +02:00
clk_reset_gen.v	FPGA: Increase clock frequency to 21 MHz	2024-08-20 13:45:00 +02:00
fw_ram.v	Verilog 2001 rule; use wires for assignments, not registers. (#139)	2023-08-16 10:44:18 +02:00
ram.v	Implement cs0 and cs1 as logic equations, not muxes	2024-03-20 14:36:55 +01:00
rom.v	Clean up code and silence warnings after linting	2024-03-20 16:39:53 +01:00