mirror of
https://github.com/tillitis/tillitis-key1.git
synced 2025-03-13 18:46:45 -04:00
3875508d1f
This is an import of the fw-2 tag of tkey-libs. We import the entire tkey-libs repo minus dot files into the tillitis-key1 repo to make it very simple not to make mistakes regarding which firmware tag depends on which tkey-libs tag, especially considering locking down with NVCM. Please see README for information about developing with another tkey-libs or how to import future tkey-libs. Since tkey-libs is now a part of the repo we also add tkey-libs to the clean_fw target.
57 lines
990 B
Plaintext
57 lines
990 B
Plaintext
/tests/*.o
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/firmware/*.o
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/firmware/firmware.bin
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/firmware/firmware.elf
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/firmware/firmware.hex
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/firmware/firmware.map
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/dhrystone/dhry.bin
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/dhrystone/dhry.elf
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/dhrystone/dhry.hex
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/dhrystone/dhry.map
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/dhrystone/testbench.vvp
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/dhrystone/testbench.vcd
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/dhrystone/testbench_nola.vvp
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/dhrystone/testbench_nola.vcd
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/dhrystone/timing.vvp
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/dhrystone/timing.txt
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/dhrystone/*.d
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/dhrystone/*.o
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/testbench.vvp
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/testbench_wb.vvp
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/testbench_ez.vvp
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/testbench_sp.vvp
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/testbench_rvf.vvp
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/testbench_synth.vvp
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/testbench.gtkw
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/testbench.vcd
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/testbench.trace
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/testbench_verilator*
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/check.smt2
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/check.vcd
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/hw/application_fpga/tkey-libs/libcommon.a
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/hw/application_fpga/tkey-libs/libcrt0.a
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/hw/application_fpga/tkey-libs/libmonocypher.a
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synth.json
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synth.txt
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synth.v
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application_fpga_par.json
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application_fpga_par.txt
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tb_application_fpga_sim.fst
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tb_application_fpga_sim.fst.hier
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tb_verilated/
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verilated/
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*.o
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*.asc
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*.bin
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*.elf
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*.map
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*.tmp
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*.hex
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!uds.hex
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!udi.hex
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.*.swp
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*.sch-bak
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*.sim
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compile_commands.json
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.cache
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