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30 lines
678 B
Verilog
30 lines
678 B
Verilog
//======================================================================
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//
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// SB_LUT4.v
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// ---------
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// Simulation model of the SB_LUT4 macro used to buil the sim target.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2023 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module SB_LUT4 (
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input wire I0,
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output wire O
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);
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parameter LUT_INIT = 16'h0;
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assign O = ~I0;
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endmodule // SB_LUT4
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//======================================================================
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// EOF SB_LUT4.v
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//======================================================================
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